Dynamic gain cell with reduced leakage
US-2025285672-A1 · Sep 11, 2025 · US
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Burg Andreas patents
Burg Andreas is listed as an inventor on 8 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Burg Andreas |
| Total patents | 8 |
| First publication | Aug 6, 2015 |
| Latest publication | Sep 11, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Fin field-effect transistor (FinFET) based semiconductor memory array having memory cells using a reduced surface area
US-12068027-B2 · Aug 20, 2024 · US
Method for reading and writing unreliable memories and a corresponding memory controller device and memory
US-12057858-B2 · Aug 6, 2024 · US
Fin Field-Effect Transistor (FinFET) Based Semiconductor Memory Array Having Memory Cells Using A Reduced Surface Area
US-2024062811-A1 · Feb 22, 2024 · US
Method For Reading And Writing Unreliable Memories And A Corresponding Memory Controller Device and Memory
US-2022122686-A1 · Apr 21, 2022 · US
Transistor gain cell with feedback
US-10002660-B2 · Jun 19, 2018 · US
Method and apparatus for low complexity spectral analysis of bio-signals
US-9760536-B2 · Sep 12, 2017 · US
Method and apparatus for low complexity spectral analysis of bio-signals
US-2015220486-A1 · Aug 6, 2015 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Ecole Polytechnique Fed Lausanne Epfl | 6 |
| Ecole Polytechnique Fed De Lausanne (Epfl) | 1 |
| Univ Bar Ilan | 1 |
| Ecole Polytech | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C11/403 | 4 |
| G11C11/419 | 3 |
| G11C11/412 | 3 |
| G11C8/16 | 3 |
| G11C5/025 | 3 |