Watertight ray triangle intersection

Patent metadata

Field	Value
Publication number	US-12067669-B2
Application number	US-202318198949-A
Country	US
Kind code	B2
Filing date	May 18, 2023
Priority date	Aug 10, 2018
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.

First claim

The invention claimed is:

1. A device including hardware circuitry configured to:
receive a query including information about a ray and a plurality of primitives;
determine, using an arithmetic unit configured to perform plural predetermined precision calculations, whether the ray intersects an edge or vertex of the primitives;
when the ray is determined to intersect an edge or vertex shared by two or more primitives, identify a single one of the two or more primitives sharing the edge or vertex based on comparing vertex values of the two or more primitives transformed into ray coordinate space;
push intersection information of the identified primitive onto a stack; and
report the intersection information stored in the stack to a processor.

2. The device of claim 1 , wherein the hardware circuitry includes a fused floating point operation unit configured to combine multiple floating-point arithmetic operations used to determine whether the ray intersects the edge or vertex of the primitive.

3. The device of claim 2 , wherein the fused floating point operation unit is configured to perform arithmetic operations using single precision floating-point numbers.

4. The device of claim 2 , wherein the fused floating point operation unit is configured to perform arithmetic operations with expanded 10-bit exponent range.

5. The device of claim 2 , wherein the hardware circuitry is configured to determine primitives of the plurality of primitives which are intersected by the ray without using double-precision floating-point arithmetic.

6. The device of claim 1 , wherein the primitives include triangles and identifying the single one of the two or more primitives sharing the edge as being intersected by the ray includes:
transforming triangle vertices into two-dimensional ray-coordinate space;
determining edge function values of post-transform triangle edges defined by transformed triangle vertices;
if all edge function values are nonzero and have a same sign, identifying the triangle as being intersected; and
if one or more of the edge function values is zero, determining whether the triangle is intersected based on comparing values of the transformed triangle vertices.

7. A system including:
memory that stores at least a portion of an acceleration data structure including a plurality of hierarchical nodes, at least one node identifying a primitive range of a virtual scene; and
hardware circuitry operatively coupled to the memory and configured to:
determine intersections between a ray defined in a ray coordinate space and primitives in the primitive range; and
when the ray is determined to intersect a vertex shared by a plurality of primitives in the primitive range, report intersection information for a single primitive among the plurality of primitives intersected by the ray based on a tie-breaking rule that compares values of vertices of the plurality of primitives sharing the vertex, transformed into the ray coordinate space.

8. The system of claim 7 , wherein the hardware circuitry further comprises a fused floating point operation unit configured to combine multiple floating-point arithmetic operations to determine whether the primitives are intersected by the ray.

9. The system of claim 8 , wherein the fused floating point operation unit is configured to perform arithmetic operations using single precision floating-point format.

10. The system of claim 8 , wherein the fused floating point operation unit is configured to perform arithmetic operations with expanded 10-bit exponent range.

11. The system of claim 7 , wherein the hardware circuitry is further configured to push onto a stack intersection information for primitives determined to be reported and report the intersection information in the stack to a processor.

12. The system of claim 7 , wherein the hardware circuitry is configured to determine primitives in the primitive range received from the memory which are intersected by the ray without using double-precision floating-point arithmetic.

13. The system of claim 7 , wherein the primitives include triangles and determining intersections between the ray and the primitives includes, for each triangle:
transforming triangle vertices into the ray coordinate space;
determining edge function values of post-transform triangle edges defined by transformed triangle vertices;
if all edge function values are nonzero and have a same sign, identifying the triangle as being intersected by the ray; and
if one or more of the edge function values is zero, determining whether the triangle is intersected based on whether another triangle shares the triangle vertices and whether one or more edge function values of the other triangle are zero.

14. The system of claim 7 , wherein system comprises a stack and the hardware circuitry is further configured to push onto the stack intersection information for primitives determined to be reported, and when the ray is determined to intersect the vertex shared by N primitives, intersection information for a single primitive of the N primitives is pushed onto the stack.

15. A system comprising:
memory that stores at least a portion of a virtual scene; and
hardware circuitry operatively coupled to the memory and configured to:
determine whether a ray intersects geometric surfaces arranged the virtual scene; and
based on determining that the ray intersects multiple geometric surfaces of the virtual scene at an edge or vertex shared by the multiple geometric surfaces, report a single surface from the multiple geometric surfaces, wherein the single surface for reporting is determined based on a comparison of vertex values of the multiple geometric surfaces projected into a two-dimensional coordinate space of the ray.

16. The system of claim 15 , wherein the hardware circuitry further comprises a fused floating point operation unit configured to combine multiple floating-point arithmetic operations to determine whether the ray intersects geometric surfaces arranged the virtual scene.

17. The system of claim 16 , wherein the fused floating point operation unit is configured to perform arithmetic operations using single precision floating-point format.

18. The system of claim 16 , wherein the fused floating point operation unit is configured to perform arithmetic operations with expanded 10-bit exponent range.

19. The system of claim 15 , wherein the hardware circuitry is configured to determine whether the ray intersects geometric surfaces arranged the virtual scene without using double-precision floating-point arithmetic.

20. The system of claim 15 , wherein the hardware circuitry includes a spatial transformer that projects geometric surfaces in virtual scone to a plane for ray intersection testing.

Assignees

• Nvidia Corp

Inventors

• Laine Samuli
• Karras Tero
• Aila Timo
• Ohannessian Robert
• Newhall Jr William Parsons
• Muthler Greg
• Kwong Ian
• Nelson Peter
• Burgess John

Classifications

• G06T15/005

  General purpose rendering architectures · CPC title

• G06V10/44

  Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersections; Connectivity analysis, e.g. of connected components · CPC title

• G06T1/60

  Memory management · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/06 Primary

  Ray-tracing · CPC title