Hardware-based obfuscation of digital data

Patent metadata

Field	Value
Publication number	US-12067091-B2
Application number	US-202117558389-A
Country	US
Kind code	B2
Filing date	Dec 21, 2021
Priority date	Dec 22, 2020
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

Some aspects of this disclosure are directed to implementing hardware-based obfuscation of digital data. For example, some aspects of this disclosure relate to a method, including performing a capture operation that loads a plurality of primary input (PI) bits into corresponding shift registers of a plurality of test data registers (TDRs) disposed on one or more digital semiconductor devices and configured to store a plurality of secret information bits. The method further includes performing a sequence of shift operations on the plurality of TDRs to obtain a plurality of output bits. The method further includes applying, by an authenticating processor, a derivation function on the plurality of output bits to extract the plurality of secret information bits thereby authenticating the one or more digital semiconductor devices.

First claim

What is claimed is:

1. A method, comprising: performing a capture operation that loads a plurality of primary input (PI) values into corresponding shift registers of a plurality of test data registers (TDRs) disposed on one or more digital semiconductor devices and configured to store a plurality of secret information bits; performing a sequence of shift operations on the plurality of TDRs to obtain a plurality of output bits; and applying, by a processor, a derivation function on the plurality of output bits to extract the plurality of secret information bits thereby authenticating the one or more digital semiconductor devices, wherein a PI value from the plurality of PI values of a first TDR of the plurality of TDRs is set to a logic high or a logic low based at least in part on the plurality of secret information bits.

2. The method of claim 1 , wherein a PI port and a primary output (PO) port of the first TDR of the plurality of TDRs are connected to a network of digital logic gates.

3. The method of claim 2 , wherein a PI of a second TDR of the plurality of TDRs is based on the PO of the first TDR of the plurality of TDRs.

4. The method of claim 2 , wherein the derivation function is based at least in part on the network of digital logic gates.

5. The method of claim 1 , wherein the applying the derivation function comprises using a bit mapping list to reorder the plurality of output bits.

6. The method of claim 5 , wherein the bit mapping list is based at least in part on addresses of the plurality of TDRs.

7. The method of claim 1 , wherein the plurality of secret information bits are a cryptographic key or a seed for a cryptographic key generator.

8. A system comprising: a memory storing instructions; and at least one processor, coupled with the memory and to execute the instructions, the instructions when executed cause the at least one processor to: perform a capture operation that loads a plurality of primary input (PI) values into corresponding shift registers of a plurality of test data registers (TDRs) disposed on one or more digital semiconductor devices and configured to store a plurality of secret information bits; perform a sequence of shift operations on the plurality of TDRs to obtain a plurality of output bits; and apply a derivation function on the plurality of output bits to extract the plurality of secret information bits, wherein a PI value from the plurality of PI values of a first TDR of the plurality of TDRs is set to a logic high or a logic low based at least in part on the plurality of secret information bits.

9. The system of claim 8 , wherein a PI port and a primary output (PO) port of the first TDR of the plurality of TDRs are connected to a network of digital logic gates.

10. The system of claim 9 , wherein the derivation function is based at least in part on the network of digital logic gates.

11. The system of claim 8 , wherein the applying the derivation function comprises using a bit mapping list to reorder the plurality of output bits.

12. The system of claim 11 , wherein the bit mapping is based at least in part on addresses of the plurality of TDRs.

13. The system of claim 8 , wherein the plurality of secret information bits are a cryptographic key or a seed for a cryptographic key generator.

14. A non-transitory computer readable medium (CRM) comprising stored instructions, which when executed by a processor, cause the processor to: perform a capture operation that loads a plurality of primary input (PI) values into corresponding shift registers of a plurality of test data registers (TDRs) disposed on one or more digital semiconductor devices and configured to store a plurality of secret information bits; and apply a derivation function on a plurality of output bits obtained from the plurality of TDRs to extract the plurality of secret information bits thereby authenticating the one or more digital semiconductor devices, wherein a PI value from the plurality of PI values of a first TDR of the plurality of TDRs is set to a logic high or a logic low based at least in part on the plurality of secret information bits.

15. The non-transitory CRM of claim 14 , wherein a PI port and a primary output (PO) port of the first TDR of the plurality of TDRs are connected to a network of digital logic gates.

16. The non-transitory CRM of claim 15 , wherein the derivation function is based at least in part on the network of digital logic gates.

17. The non-transitory CRM of claim 14 , wherein the applying the derivation function comprises using a bit mapping list to reorder the plurality of output bits.

Assignees

• Synopsys Inc

Inventors

• Cron Adam David
• Elias Andrew
• Reddy Bandi Chandra Sekhar
• Borza Michael

Classifications

• G06F21/73

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• G06F21/78

  to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

• G06F21/602

  Providing cryptographic facilities or services · CPC title

• G06F21/14 Primary

  against software analysis or reverse engineering, e.g. by obfuscation · CPC title

• G06F11/3668 Primary

  Testing of software · CPC title