Method and apparatus for securing access to an integrated circuit

Patent metadata

Field	Value
Publication number	US-2016149697-A1
Application number	US-201414551170-A
Country	US
Kind code	A1
Filing date	Nov 24, 2014
Priority date	Nov 24, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A method and apparatus are described securely testing an integrated circuit (IC). When the IC is powered on, a first bit stream including unencrypted data bits and encrypted data bits is received by the IC, a second bit stream is generated based on a pseudorandom pattern, a third bit stream is generated by convolving the first bit stream with the second bit stream, the third bit stream is fed to at least one selected test data register (TDR), (i.e., a shift register), in the IC, a fourth bit stream is generated by delaying the second bit stream, and a fifth bit stream is generated by convolving a sixth bit stream output by the at least one selected TDR with the fourth bit stream. The fifth bit stream includes the same unencrypted data bits and encrypted data bits as the first bit stream.

First claim

What is claimed is:

1 . A method of securely testing an integrated circuit (IC), the method comprising:
receiving a first bit stream including unencrypted data bits and encrypted data bits; generating a second bit stream based on a pseudorandom pattern; generating a third bit stream by convolving the first bit stream with the second bit stream; feeding the third bit stream to at least one selected test data register (TDR) in the IC; generating a fourth bit stream by delaying the second bit stream; and generating a fifth bit stream by convolving a sixth bit stream output by the at least one selected TDR with the fourth bit stream, wherein the fifth bit stream includes the same unencrypted data bits and encrypted data bits as the first bit stream.

2 . The method of claim 1 wherein a first exclusive- or (XOR) gate in the IC is used to convolve the first bit stream with the second bit stream.

3 . The method of claim 2 wherein a second XOR gate in the IC is used to convolve the sixth bit stream output by the at least one selected TDR with the fourth bit stream.

4 . The method of claim 3 wherein the first XOR gate is configured to selectively invert the bits in the first bit stream based on the second bit stream.

5 . The method of claim 4 wherein the second XOR gate is configured to selectively invert the bits in the sixth bit stream output by the at least one selected TDR based on the fourth bit stream.

6 . The method of claim 1 wherein the at least one selected TDR is selected from a plurality of concatenated TDRs.

7 . The method of claim 1 wherein bits in the first bit stream that are destined to be updated in the at least one selected TDR are encrypted, and all other bits in the first bit stream are unencrypted.

8 . The method of claim 1 wherein bits in the first bit stream that are captured by the at least one selected TDR are unencrypted.

9 . A semiconductor device comprising:
an input configured to receive a first bit stream including unencrypted data bits and encrypted data bits; a pseudorandom pattern generator (PRPG) configured to generate a second bit stream; a first exclusive- or (XOR) gate configured to generate a third bit stream by convolving the first bit stream with the second bit stream; a test data register (TDR) unit configured to receive the third bit stream; a delay unit configured to generate a fourth data stream by delaying the second bit stream; and a second XOR gate configured to generate a fifth bit stream by convolving a sixth bit stream output by the at least one selected TDR with the fourth bit stream, wherein the fifth bit stream includes the same unencrypted data bits and encrypted data bits as the first bit stream.

10 . The semiconductor device of claim 9 wherein the first XOR gate is coupled to the PRPG, the delay unit and an input to the TDR unit.

11 . The semiconductor device of claim 9 wherein the second XOR gate is coupled to the delay unit and an output from the TDR unit.

12 . The semiconductor device of claim 9 wherein the second bit stream is generated by the PRPG based on a selected characteristic sequence and a selected seed.

13 . The semiconductor device of claim 9 wherein a length of the TDR unit is adjustable.

14 . The semiconductor device of claim 9 wherein the first bit stream consists of logic 1 bits and logic 0 bits.

15 . The semiconductor device of claim 9 wherein the first XOR gate is configured to selectively invert the bits in the first bit stream based on the second bit stream.

16 . The semiconductor device of claim 15 wherein the second XOR gate is configured to selectively invert the bits in the sixth bit stream based on the second bit stream.

17 . The semiconductor device of claim 15 wherein bits in the first bit stream that are destined to be updated in the at least one selected TDR are encrypted, and all other bits in the first bit stream are unencrypted.

18 . The semiconductor device of claim 15 wherein bits in the first bit stream that are captured by the at least one selected TDR are unencrypted.

19 . A non-transitory computer-readable storage medium configured to store a set of instructions used for manufacturing a semiconductor device, wherein the semiconductor device comprises:
an input configured to receive a first bit stream including unencrypted data bits and encrypted data bits; a pseudorandom pattern generator (PRPG) configured to generate a second bit stream; a first exclusive- or (XOR) gate configured to generate a third bit stream by convolving the first bit stream with the second bit stream; a test data register (TDR) unit configured to receive the third bit stream; a delay unit configured to generate a fourth data stream by delaying the second bit stream; and a second XOR gate configured to generate a fifth bit stream by convolving a sixth bit stream output by the at least one selected TDR with the fourth bit stream, wherein the fifth bit stream includes the same unencrypted data bits and encrypted data bits as the first bit stream.

20 . The non-transitory computer-readable storage medium of claim 19 wherein the instructions are Verilog data instructions or hardware description language (HDL) instructions.

Assignees

• Advanced Micro Devices Inc

Inventors

• Doege Jason

Classifications

• H04L9/0662 Primary

  with particular pseudorandom sequence generator · CPC title

• H04L2209/26

  Testing cryptographic entity, e.g. testing integrity of encryption key or encryption algorithm · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title