Interface for memory readout from a memory component in the event of fault

Patent metadata

Field	Value
Publication number	US-12066957-B2
Application number	US-202318130355-A
Country	US
Kind code	B2
Filing date	Apr 3, 2023
Priority date	Oct 7, 2015
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

First claim

We claim:

1. A memory device, comprising:
memory core circuitry to store data;
a primary interface circuit including a data interface for coupling to multiple data paths and a command/address (C/A) interface for coupling to a command/address path, the primary interface to provide access to the data stored in the memory core circuitry during a normal mode of operation; and
a secondary interface that is independent from the primary interface, the secondary interface to selectively provide access to the data stored in the memory core circuitry during a fault mode of operation.

2. The memory device of claim 1 , wherein:
the secondary interface includes a serial interface for coupling to a serial bus.

3. The memory device of claim 2 , wherein:
the serial interface includes a serial port for coupling to at least one other memory device.

4. The memory device of claim 2 , wherein the serial interface further comprises:
an input serial port; and
an output serial port.

5. The memory device of claim 4 , wherein:
the input serial port receives an access request to access a portion of the data in the memory core circuitry; and
the output serial port transfers the portion of the data as a serialized output stream.

6. The memory device of claim 4 , wherein:
the input serial port receives serialized data from a second memory device; and
the output serial port transfers the serialized data as a serialized output stream.

7. The memory device of claim 1 , further comprising:
serial control circuitry to control operation from the normal mode of operation to the fault mode of operation.

8. The memory device of claim 1 , embodied as a dynamic random access memory (DRAM) device.

9. The memory device of claim 1 , further comprising:
interface selection circuitry to select the primary interface to access the memory core circuitry during the normal mode of operation, and to select the secondary interface to access the memory core circuitry during the fault mode of operation.

10. The memory device of claim 1 , wherein:
the primary interface includes a parallel interface for coupling to a parallel bus.

11. An integrated circuit (IC) dynamic random access memory (DRAM) device, comprising:
memory core circuitry to store data;
a parallel interface including a data interface for coupling to multiple data paths and a command/address (C/A) interface for coupling to a command/address path, the parallel interface to provide access to the data stored in the memory core circuitry during a normal mode of operation; and
a serial interface that is independent from the parallel interface, the serial interface to selectively provide access to the data stored in the memory core circuitry during a fault mode of operation.

12. The IC DRAM device of claim 11 , wherein the serial interface further comprises:
an input serial port; and
an output serial port.

13. The IC DRAM device of claim 12 , wherein:
the input serial port receives an access request to access a portion of the data in the memory core circuitry; and
the output serial port transfers the portion of the data as a serialized output stream.

14. The IC DRAM device of claim 12 , wherein:
the input serial port receives serialized data from a second memory device; and
the output serial port transfers the serialized data as a serialized output stream.

15. The IC DRAM device of claim 11 , further comprising:
serial control circuitry to control operation from the normal mode of operation to the fault mode of operation.

16. The IC DRAM device of claim 11 , further comprising:
interface selection circuitry to select the parallel interface to access the memory core circuitry during the normal mode of operation, and to select the serial interface to access the memory core circuitry during the fault mode of operation.

17. A method of operating an integrated circuit (IC) memory device, comprising
providing access, via a parallel interface, to data stored in memory core circuitry during a normal mode of operation, the parallel interface including a data interface for coupling to multiple data paths and a command/address (C/A) interface for coupling to a command/address path; and
selectively providing access, via a serial interface, to the data stored in the memory core circuitry during a fault mode of operation, the serial interface being independent from the parallel interface.

18. The method of claim 17 , wherein the selectively providing access further comprises:
receiving an access command via the serial interface to retrieve the data stored in the memory core circuitry; and
transferring the accessed data off-chip.

19. The method of claim 17 , wherein the selectively providing access further comprises:
receiving, via an input port of the serial interface, second data from a different memory device; and
transferring the second data off-chip via an output port of the serial interface.

20. The method of claim 17 , wherein:
the providing access, via the parallel interface, to the data stored in the memory core circuitry is carried out in compliance with a dynamic random access memory (DRAM) protocol.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Wright Kenneth L

Classifications

• G06F11/0784

  Routing of error reports, e.g. with a specific transmission path or data flow · CPC title

• G06F11/2007

  using redundant communication media · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title