Interface for memory readout from a memory component in the event of fault

Patent metadata

Field	Value
Publication number	US-11625346-B2
Application number	US-202217715379-A
Country	US
Kind code	B2
Filing date	Apr 7, 2022
Priority date	Oct 7, 2015
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

First claim

We claim:

1. A memory module, comprising:
a substrate;
multiple memory devices mounted to the substrate;
a parallel interface including multiple data paths and a command/address path to access groups of the multiple memory devices in parallel during a normal mode of operation;
a serial interface that is independent from the parallel interface, the serial interface including a serial bus formed on the substrate and coupled to each of the multiple memory devices and to access a selected one of the multiple memory devices during a fault mode of operation.

2. The memory module of claim 1 , wherein:
the serial interface accesses data from the selected one of the multiple memory devices via a serial port formed on the selected one of the multiple memory devices.

3. The memory module of claim 2 , wherein:
the serial bus is coupled to each of the multiple memory devices via a daisy-chain configuration.

4. The memory module of claim 1 , further comprising:
serial control circuitry to control operation from the normal mode of operation to the fault mode of operation.

5. The memory module of claim 4 , further comprising:
a buffer disposed on the substrate; and
wherein the serial control circuitry is formed in the buffer.

6. The memory module of claim 1 , further comprising:
fault detection circuitry; and
wherein the fault mode of operation is initiated based on detection of a fault by the fault detection circuitry.

7. The memory module of claim 6 , wherein the fault detection circuitry comprises:
error coding circuitry to detect an error via an error code.

8. The memory module of claim 1 , further comprising:
during the fault mode of operation,
the serial interface is operative to retrieve data stored in the selected one of the multiple memory devices, and to transfer the accessed data off-chip.

9. The memory module of claim 8 , further comprising:
substitute storage to store the data retrieved from the selected one of the multiple memory devices by the serial interface during the fault mode of operation.

10. The memory module of claim 9 , wherein the substitute storage comprises:
at least one spare memory device other than the multiple memory devices.

11. A dynamic random access memory (DRAM) memory module, comprising:
multiple DRAM memory devices;
a parallel interface including multiple data paths and a command/address path to access groups of the multiple DRAM memory devices in parallel during a normal mode of operation;
a serial interface that is independent from the parallel interface, the serial interface including a serial bus coupled to each of the multiple memory devices via respective serial ports, the serial interface to access a selected one of the multiple memory devices during a fault mode of operation.

12. The DRAM memory module of claim 11 , further comprising:
a substrate;
wherein the multiple memory devices are disposed on the substrate; and
wherein the serial bus is formed on the substrate.

13. The DRAM memory module of claim 11 , wherein:
the serial bus is coupled to each of the multiple DRAM memory devices via a daisy-chain configuration.

14. The DRAM memory module of claim 11 , further comprising:
serial control circuitry to control operation from the normal mode of operation to the fault mode of operation.

15. The DRAM memory module of claim 14 , further comprising:
a buffer; and
wherein the serial control circuitry is formed in the buffer.

16. The DRAM memory module of claim 11 , further comprising:
fault detection circuitry; and
wherein the fault mode of operation is initiated based on detection of a fault by the fault detection circuitry.

17. A memory module, comprising
a substrate;
multiple memory devices mounted to the substrate;
a parallel interface including multiple data paths and a command/address path for coupling to a memory controller to access groups of the multiple memory devices in parallel;
a serial interface that is independent from the parallel interface, the serial interface including a serial bus formed on the substrate and coupled to each of the multiple memory devices, the serial interface configured to access a selected one of the multiple memory devices that is inaccessible by the parallel interface.

18. The memory module of claim 17 , wherein:
the serial interface is operative to retrieve data stored in the selected one of the multiple memory devices, and to transfer the accessed data off-chip.

19. The memory module of claim 18 , further comprising:
substitute storage to store the data retrieved from the selected one of the multiple memory devices by the serial interface.

20. The memory module of claim 19 , wherein the substitute storage comprises:
at least one spare memory device other than the multiple memory devices.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Wright Kenneth L

Classifications

• G06F11/0784

  Routing of error reports, e.g. with a specific transmission path or data flow · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title