Read only memory

Patent metadata

Field	Value
Publication number	US-12063775-B2
Application number	US-202318484906-A
Country	US
Kind code	B2
Filing date	Oct 11, 2023
Priority date	Dec 18, 2020
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.

First claim

What is claimed is:

1. A read-only memory (ROM), comprising:
a plurality of memory cells, each of the plurality of memory cells comprising a rewritable first transistor and a rewritable second transistor, an insulated gate of the rewritable first transistor connected to an insulated gate of the rewritable second transistor,
wherein the rewritable first transistor comprises:
a first insulating layer deposited on a semiconductor structure;
a first gate layer deposited on the first insulating layer;
a second insulating layer deposited on the first gate layer; and
a second gate layer deposited on the second insulating layer, and

wherein the rewritable second transistor comprises:
the first insulating layer deposited on a well arranged between the semiconductor structure and the first insulating layer;
the first gate layer deposited on the first insulating layer;
the second insulating layer deposited on the first gate layer; and
the second gate layer deposited on the second insulating layer.

2. The ROM of claim 1 , wherein each of the rewritable first transistor and the rewritable second transistor is a metal-oxide-semiconductor (MOS) transistor.

3. The ROM of claim 1 , wherein each of the rewritable first transistor and the rewritable second transistor is an N-channel MOS transistor.

4. The ROM of claim 1 , wherein the semiconductor structure comprises a p-type doped semiconductor substrate stacked on an n-doped semiconductor layer, wherein the n-doped semiconductor layer is stacked on a p-doped semiconductor layer.

5. The ROM of claim 4 , wherein the rewritable first transistor is separated from the rewritable second transistor by a semiconductor trench formed in the p-type doped semiconductor substrate.

6. The ROM of claim 5 , wherein the n-doped semiconductor layer includes a portion extending into the p-type doped semiconductor substrate.

7. The ROM of claim 6 , wherein the semiconductor trench extends through the p-type doped semiconductor substrate to the portion of the n-doped semiconductor layer extending into the p-type doped semiconductor substrate.

8. A read-only memory (ROM), comprising:
a plurality of memory cells, each of the plurality of memory cells comprising a rewritable first transistor and a rewritable second transistor, an insulated gate of the rewritable first transistor connected to an insulated gate of the rewritable second transistor, wherein each of the rewritable first transistor and the rewritable second transistor includes:
a first insulating layer deposited on a semiconductor structure, the semiconductor structure comprising a p-type doped semiconductor substrate stacked on an n-doped semiconductor layer, the n-doped semiconductor layer stacked on a p-doped semiconductor layer, wherein uniquely for each rewritable second transistor, the first insulating layer, for the rewritable second transistor is deposited on a well arranged between the semiconductor structure and the first insulating layer;
a first gate layer deposited on the first insulating layer;
a second insulating layer deposited on the first gate layer; and
a second gate layer deposited on the second insulating layer.

9. The ROM of claim 8 , wherein each of the rewritable first transistor and the rewritable second transistor is a metal-oxide-semiconductor (MOS) transistor.

10. The ROM of claim 8 , wherein each of the rewritable first transistor and the rewritable second transistor is an N-channel MOS transistor.

11. The ROM of claim 8 , wherein the rewritable first transistor is separated from the rewritable second transistor by a semiconductor trench formed in the p-type doped semiconductor substrate.

12. The ROM of claim 11 , wherein the n-doped semiconductor layer includes a portion extending into the p-type doped semiconductor substrate.

13. The ROM of claim 12 , wherein the semiconductor trench extends through the p-type doped semiconductor substrate to the portion of the n-doped semiconductor layer extending into the p-type doped semiconductor substrate.

14. The ROM of claim 8 , wherein the well adjusts a threshold voltage of the rewritable second transistor.

15. A method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells, each of the plurality of memory cells comprising a rewritable first transistor and a rewritable second transistor, an insulated gate of the rewritable first transistor connected to an insulated gate of the rewritable second transistor, the method comprising:
successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well formed between an associated first insulating layer and the semiconductor structure, and wherein the first insulating layer is in direct contact with the semiconductor structure; and
successively depositing a second insulating layer and a second gate layer.

16. The method of claim 15 , wherein each of the rewritable first transistor and the rewritable second transistor is a metal-oxide-semiconductor (MOS) transistor.

17. The method of claim 15 , wherein each of the rewritable first transistor and the rewritable second transistor is an N-channel MOS transistor.

18. The method of claim 15 , wherein the semiconductor structure comprises a p-type doped semiconductor substrate stacked on an n-doped semiconductor layer, wherein the n-doped semiconductor layer is stacked on a p-doped semiconductor layer, and wherein the rewritable first transistor is separated from the rewritable second transistor by a semiconductor trench formed in the p-type doped semiconductor substrate.

19. The method of claim 18 , wherein the n-doped semiconductor layer includes a portion extending into the p-type doped semiconductor substrate, and wherein the semiconductor trench extends through the p-type doped semiconductor substrate to the portion of the n-doped semiconductor layer extending into the p-type doped semiconductor substrate.

20. The method of claim 15 , wherein the well adjusts a threshold voltage of the rewritable second transistor.

Assignees

• St Microelectronics Rousset
• St Microelectronics Crolles 2 Sas

Inventors

• Marzaki Abderrezak
• Lisart Mathieu
• Froment Benoit

Classifications

• H10W42/40

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• H10D30/6894

  having one gate at least partly in a trench · CPC title

• H10D64/035 Primary

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• H10B41/30

  characterised by the memory core region · CPC title