Split gate flash memory cells with a trench-formed select gate

Patent metadata

Field	Value
Publication number	US-11404549-B2
Application number	US-202017026436-A
Country	US
Kind code	B2
Filing date	Sep 21, 2020
Priority date	Sep 21, 2020
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

Structures for a split gate flash memory cell and methods of forming a structure for a split gate flash memory cell. A trench is formed in a semiconductor substrate. First and second source/drain regions are formed in the semiconductor substrate. A first gate is laterally positioned between the trench and the second source/drain region, and a second gate includes a portion inside the trench. The first source/drain region is located in the semiconductor substrate beneath the trench. A dielectric layer is positioned between the portion of the second gate inside the trench and the semiconductor substrate.

First claim

What is claimed is:

1. A structure for a flash memory cell, the structure comprising:
a semiconductor substrate including a trench;
a first source/drain region and a second source/drain region in the semiconductor substrate, the first source/drain region located beneath the trench;
a well in a portion of the semiconductor substrate surrounding the trench, the well providing a channel region disposed between the first source/drain region and the second source/drain region;
a first gate laterally positioned between the trench and the second source/drain region;
a second gate including a first portion inside the trench and a second portion above the first portion, the second portion of the second gate extending laterally to overlap with the first gate;
a first dielectric layer including a first portion inside the trench, the first portion of the first dielectric layer positioned between the first portion of the second gate and the semiconductor substrate; and
a second dielectric layer positioned between the first gate and the first dielectric layer.

2. The structure of claim 1 wherein the second dielectric layer fully covers the first gate.

3. The structure of claim 1 wherein the first gate includes a first portion and a second portion, the first dielectric layer covers the first portion of the first gate, and the first dielectric layer and the second dielectric layer cover the second portion of the first gate with the second dielectric layer disposed between the first dielectric layer and the second portion of the first gate.

4. The structure of claim 3 wherein the first portion of the first gate is positioned adjacent to the trench.

5. The structure of claim 1 wherein the first portion of the second gate includes a first section and a second section, and further comprising:
an isolation pillar positioned between the first section and the second section of the second gate, the isolation pillar comprised of a dielectric material.

6. The structure of claim 1 wherein the semiconductor substrate has a top surface, and the first gate is positioned over the top surface of the semiconductor substrate.

7. The structure of claim 1 wherein the semiconductor substrate has a top surface, and the first portion of the second gate is positioned fully beneath the top surface of the semiconductor substrate.

8. The structure of claim 1 wherein the first dielectric layer includes a second portion positioned between the second portion of the second gate and the first gate.

9. The structure of claim 8 wherein the semiconductor substrate has a top surface, and the second portion of the second gate is positioned above the top surface of the semiconductor substrate.

10. The structure of claim 8 wherein the first gate surrounds the second portion of the second gate.

11. The structure of claim 1 wherein the first portion of the second gate includes a first section and a second section, and further comprising:
an insulating separator positioned between the first section and the second section of the second gate.

12. The structure of claim 1 wherein the second gate is configured to be biased to program the flash memory cell and biased to erase the flash memory cell.

13. The structure of claim 1 wherein the first portion of the second gate and the first portion of the first dielectric layer fully fill a space inside the trench.

14. The structure of claim 1 wherein the first source/drain region extends along a length of the trench and the first portion of the second gate.

15. A method of forming a structure for a flash memory cell, the method comprising:
forming a trench in a semiconductor substrate;
forming a first source/drain region and a second source/drain region in the semiconductor substrate;
forming a well in a portion of the semiconductor substrate that surrounds the trench, wherein the well provides a channel region disposed between the first source/drain region and the second source/drain region;
forming a first gate laterally positioned between the trench and the second source/drain region;
forming a first dielectric layer including a portion inside the trench; and
forming a second gate including a first portion inside the trench and a second portion above the first portion, wherein the second portion of the second gate extends laterally to overlap with the first gate,
wherein a second dielectric layer is positioned between the first gate and the first dielectric layer, the first source/drain region is located in the semiconductor substrate beneath the trench, and the portion of the first dielectric layer is positioned between the portion of the second gate and the semiconductor substrate.

16. The method of claim 15 wherein forming the first gate laterally positioned between the trench and the second source/drain region comprises:
patterning a layer stack including a layer comprised of a material to form the first gate.

17. The method of claim 15 wherein forming the first source/drain region and the second source/drain region in the semiconductor substrate comprises:
implanting ions into the semiconductor substrate beneath a bottom of the trench to form the first source/drain region.

18. The method of claim 15 wherein forming the second gate including the portion inside the trench comprises:
after forming the first dielectric layer, depositing a material on the first dielectric layer that fills the trench; and
patterning the material to form the second gate.

19. The method of claim 16 wherein the second dielectric layer is patterned when the material is patterned, the second dielectric layer is positioned over the first gate, and further comprising;
laterally recessing the second dielectric layer before forming the first dielectric layer and the second gate.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Cai Xinshu
• Tan Shyue Seng
• Toh Eng Huat
• Quek Kiok Boone Elgin

Classifications

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D62/151 Primary

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/683

  programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title