Electronic device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12062832-B2
Application number	US-202117383403-A
Country	US
Kind code	B2
Filing date	Jul 22, 2021
Priority date	Jul 31, 2018
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

A method of manufacturing an electronic device includes providing a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer, and removing at least a portion of each of the two conductive layers to respectively form an antenna pattern and a circuit pattern of a chip package at the two opposite surfaces of the core dielectric layer.

First claim

What is claimed is:

1. A method of manufacturing an electronic device, comprising:
forming a composite structure, wherein the composite structure comprises:
a core dielectric layer comprising a first surface, a second surface opposite to the first surface, and an alignment mark;
a first conductive layer formed on the first surface of the core dielectric layer; and
a second conductive layer formed on the second surface of the core dielectric layer;

patterning the first conductive layer and the second conductive layer to respectively form an antenna pattern and a circuit pattern through the alignment mark;
encapsulating the antenna pattern to form an antenna package;
encapsulating a plurality of semiconductor chips disposed on the circuit pattern to form a chip package, wherein the semiconductor chips are electrically coupled to the circuit pattern and the antenna pattern; and
cutting the antenna package, the chip package, and the core dielectric layer disposed therebetween into a plurality of electronic devices.

2. The method of claim 1 , wherein patterning the first conductive layer comprises:
forming a patterned mask on the first conductive layer, wherein the patterned mask exposes a portion of the first conductive layer, and
removing the portion of the first conductive layer to form the antenna pattern with a first undercut.

3. The method of claim 2 , wherein forming the antenna pattern with the first undercut comprises:
performing a wet etching process which is selective to a material of the first conductive layer.

4. The method of claim 1 , wherein patterning the second conductive layer comprises:
forming a patterned dielectric layer on the second conductive layer, wherein the patterned dielectric layer exposes a portion of the second conductive layer, and
removing the portion of the second conductive layer to form the circuit pattern with a second undercut.

5. The method of claim 4 , wherein forming the circuit pattern with the second undercut comprises:
performing a wet etching process which is selective to a material of the second conductive layer.

6. The method of claim 1 , wherein patterning the second conductive layer comprises:
thinning the second conductive layer to form a thinned conductive layer; and
removing a portion of the thinned conductive layer to form the circuit pattern.

7. The method of claim 1 , wherein forming the chip package comprises:
attaching a back surface of each of the plurality of semiconductor chips to the core dielectric layer by forming an attaching layer between the back surface and the core dielectric layer, wherein during the attaching, the attaching layer fills a spacing of the circuit pattern to be in contact with the core dielectric layer.

8. The method of claim 1 , wherein forming the chip package comprises:
attaching a conductive element to the circuit pattern through a conductive joint, wherein the conductive element is a T-shaped post.

9. The method of claim 1 , wherein the alignment mark of the core dielectric layer comprises a plurality of recesses distributed along a periphery of the core dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Pei-Hsuan
• Hsieh Ching-Hua
• Hwang Chien-Ling
• Chiu Yu-Ting
• Kuo Jui-Chang

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title