Fabrication of all-solid-state energy storage devices

Patent metadata

Field	Value
Publication number	US-12062761-B2
Application number	US-202117321555-A
Country	US
Kind code	B2
Filing date	May 17, 2021
Priority date	Jan 2, 2019
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

A semiconductor device structure and method for forming the same is disclosed. The structure incudes a silicon substrate having at least one trench disposed therein. An electrical and ionic insulating layer is disposed over at least a top surface of the substrate. A plurality of energy storage device layers is formed within the one trench. The plurality of layers includes at least a cathode-based active electrode having a thickness of, for example, at least 100 nm and an internal resistance of, for example, less than 50 Ohms/cm 2 . The method includes forming at least one trench in a silicon substrate. An electrical and ionic insulating layer(s) is formed and disposed over at least a top surface of the silicon substrate. A plurality of energy storage device layers is formed within the trench. Each layer of the plurality of energy storage device layers is independently processed and integrated into the trench.

First claim

What is claimed is:

1. A semiconductor device structure comprising:
a silicon substrate having at least one trench disposed therein, the at least one trench providing an energy storage device containment feature;
an electrical and ionic insulating layer comprising a first portion disposed over a top surface of the silicon substrate and a second portion in contact with sidewalls of the at least one trench; and
a plurality of energy storage device layers within the at least one trench, wherein each energy storage device layer of the plurality of energy storage device layers is in direct contact with the second portion of the electrical and ionic insulating layer, the plurality of energy storage device layers comprising at least a composite cathode-based active electrode having a thickness of at least 100 nm and an internal resistance of less than 150 Ohms/cm 2 .

2. The semiconductor device structure of claim 1 , wherein the plurality of energy storage device layers further comprises at least:
an anode-based active electrode;
an electrolyte layer disposed over the anode-based active electrode, wherein the electrolyte layer is comprised of a material having an initial powder-based composition comprising a glass transition state; and
a current collector layer disposed over the composite cathode-based active electrode.

3. The semiconductor device structure of claim 1 , wherein the composite cathode-based active electrode comprises one or more of:
a first layer comprising 90% electrolyte material, where a remainder of the first layer is comprised of at least one of cathode active material or electrically conductive material;
a second layer comprising 80% electrolyte material, where a remainder of the second layer is comprised of at least one of cathode active material or electrically conductive material;
a third layer comprising 60% electrolyte material, where a remainder of the third layer is comprised of at least one of cathode active material or electrically conductive material;
a fourth layer comprising 40% electrolyte material, where a remainder of the fourth layer is comprised of at least one of cathode active material or electrically conductive material;
a fifth layer comprising 20% electrolyte material, where a remainder of the fifth layer is comprised of at least one of cathode active material or electrically conductive material;
a sixth layer comprising 10% electrolyte material, where a remainder of the sixth layer is comprised of at least one of cathode active material or electrically conductive material; and
a seventh layer or layers comprising 0% electrolyte material, where a remainder of the seventh layer is comprised of at least one of cathode active material or electrically conductive material.

4. The semiconductor device structure of claim 1 , further comprising:
one or more vias formed within a base of the at least one trench, wherein each via of the one or more vias comprises metal material.

5. The semiconductor device structure of claim 1 , further comprising an encapsulation layer disposed over the first portion of the electrical and ionic insulating layer.

6. The semiconductor device structure of claim 5 , wherein the encapsulation layer is co-planar with a current collector layer disposed over the plurality of energy storage device layers.

7. The semiconductor device structure of claim 5 , further comprising a current collector layer disposed over the plurality of energy storage device layers.

8. The semiconductor device structure of claim 7 , wherein a first portion of the current collector layer extends below a top surface of the silicon substrate and a second portion of the current collector layer extends above the top surface of the silicon substrate.

9. The semiconductor device structure of claim 7 , wherein the plurality of energy storage device layers comprises a charge hosting material layer in contact with the silicon substrate and an anode material layer disposed on and in contact with the charge hosting material layer.

10. The semiconductor device structure of claim 7 , wherein the plurality of energy storage device layers comprises a charge hosting material layer in contact with an anode material layer.

11. The semiconductor device structure of claim 10 , further comprising a current collector layer disposed over and in contact with the charge hosting material layer.

12. A semiconductor device structure comprising:
a silicon substrate having at least one trench disposed therein, the at least one trench providing an energy storage device containment feature;
an electrical and ionic insulating layer comprising a first portion disposed over a top surface of the silicon substrate and a second portion in contact with sidewalls of the at least one trench; and
a plurality of energy storage device layers within the at least one trench and in contact with the second portion of the electrical and ionic insulating layer, the plurality of energy storage device layers comprising a layer in direct contact with the silicon substrate and also comprising at least a composite cathode-based active electrode.

Assignees

• IBM

Inventors

• Collins John
• Krishnan Mahadevaiyer
• Bedell Stephen
• Pacquette Adele L
• Papalia John
• Todorov Teodor

Classifications

• H01M50/555

  Window-shaped terminals · CPC title

• H01M10/0525

  Rocking-chair batteries, i.e. batteries with lithium insertion or intercalation in both electrodes; Lithium-ion batteries · CPC title

• Y02P70/50

  Manufacturing or production processes characterised by the final manufactured product · CPC title

• H01M10/0565

  Polymeric materials, e.g. gel-type or solid-type · CPC title

• H01M10/0562

  Solid materials · CPC title