Memory device

Patent metadata

Field	Value
Publication number	US-12062606-B2
Application number	US-202117337212-A
Country	US
Kind code	B2
Filing date	Jun 2, 2021
Priority date	Oct 14, 2020
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

A memory device includes: a memory cell region including gate electrodes spaced apart from each other on a first semiconductor substrate to be stacked, and channel structures; and a peripheral circuit region including upper metal lines disposed above a second semiconductor substrate, disposed below the memory cell region. The first semiconductor substrate includes first regions, having a first value corresponding to a distance between the first semiconductor substrate and the upper metal lines, and second regions having a second value, lower than the first value. A reference voltage for operating the memory device is transmitted to at least one of the first upper metal lines, disposed below the first region. Accordingly, coupling capacitance for a significant signal may be reduced while maintaining a length of a connection portion and the magnitude of resistance of a common source line. Furthermore, an error rate of the memory device may be reduced.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell region including a first semiconductor substrate, gate electrodes spaced apart from each other on the first semiconductor substrate to be stacked in a first direction, perpendicular to an upper surface of the first semiconductor substrate, and channel structures penetrating through the gate electrodes and electrically connected to the first semiconductor substrate; and
a peripheral circuit region including a second semiconductor substrate disposed below the memory cell region, and a plurality of upper metal lines disposed above the second semiconductor substrate, with each of the upper metal lines has an upper surface disposed at a first height and extending in a second direction, parallel to an upper surface of the second semiconductor substrate,
wherein the first semiconductor substrate includes first regions having a first distance between a lower surface of the first semiconductor substrate and an upper surface of first upper metal lines of the plurality of upper metal lines, and second regions having a second distance between the lower surface of the first semiconductor substrate and an upper surface of second upper metal lines of the plurality of upper metal lines, the second distance is shorter than the first distance, and
wherein the first upper metal lines are disposed below the first regions, and the second upper metal lines are disposed below the second regions, and at least one of the first upper metal lines is configured to transmit a reference voltage for operating the memory cell region and the peripheral circuit region.

2. The memory device of claim 1 , wherein the reference voltage includes a bandgap reference (BGR) signal.

3. The memory device of claim 1 , wherein the first height includes a height of an upper surface of an uppermost layer, among layers on which metal lines are disposed.

4. The memory device of claim 1 , wherein the first regions and the second regions are laterally arranged in the first semiconductor substrate, and are alternately disposed in a third direction perpendicular to the second direction.

5. The memory device of claim 4 , wherein a distance between a pair of first regions adjacent to each other in the third direction, among the first regions, is the same as a distance between a pair of upper metal lines adjacent to each other in the third direction, among the plurality of upper metal lines.

6. The memory device of claim 4 , wherein at least two of the plurality of upper metal lines are disposed below a portion between a pair of first regions adjacent to each other in the third direction, among the first regions.

7. The memory device of claim 4 , wherein a pair of first regions adjacent to each other, among the first regions, and a pair of second regions adjacent to each other, among the second regions, each have the same length in the third direction.

8. The memory device of claim 4 , wherein at least some of the first regions and the second regions have different lengths in the third direction.

9. The memory device of claim 8 , wherein at least one of a pair of first regions adjacent to each other, among the first regions, and a pair of second regions adjacent to each other, among the second regions, have different lengths in the third direction.

10. The memory device of claim 8 , wherein at least one of the first regions is adjacent to a second region having the same length on a first side in the third direction, and is adjacent to a second region having a different length on a second side in the third direction.

11. The memory device of claim 1 , wherein the number of the first regions is the same as the number of the second regions.

12. The memory device of claim 1 , wherein
a sum of lengths of the first regions is the same as a sum of lengths of the second regions, in a third direction parallel to the first semiconductor substrate and the second semiconductor substrate and perpendicular to the second direction.

13. The memory device of claim 1 , wherein the first semiconductor substrate further includes third regions having a third distance between a lower surface of the first semiconductor substrate and an upper surface of third upper metal lines of the plurality of upper metal lines, the third distance being between the first distance and the second distance, and
the first semiconductor substrate has an inclined lower surface in the third regions.

14. The memory device of claim 1 , wherein the first semiconductor substrate further includes third regions having a third distance between a lower surface of the first semiconductor substrate and an upper surface of third upper metal lines of the plurality of upper metal lines, the third distance being between the first distance and the second distance, and
the first semiconductor substrate has a lower surface having curvature in the third regions.

15. The memory device of claim 1 , wherein a length of the first regions in a third direction, parallel to the first semiconductor substrate and the second semiconductor substrate and perpendicular to the second direction, is determined based on the first distance and the second distance.

16. A memory device comprising:
a memory cell region including a first semiconductor substrate, gate electrodes spaced apart from each other on the first semiconductor substrate to be stacked in a first direction, perpendicular to an upper surface of the first semiconductor substrate, and channel structures penetrating through the gate electrodes and disposed in a recessed portion of the first semiconductor substrate; and
a peripheral circuit region including a second semiconductor substrate disposed below the memory cell region, a plurality of lower metal lines disposed above the second semiconductor substrate at a predetermined height to extend in a second direction, parallel to an upper surface of the second semiconductor substrate, and a plurality of upper metal lines disposed between the plurality of lower metal lines and the first semiconductor substrate to extend in a third direction, parallel to an upper surface of the second semiconductor substrate and perpendicular to the second direction,
wherein the first semiconductor substrate includes first regions, having a first distance between a lower surface of the first semiconductor substrate and an upper surface of first upper metal lines of the plurality of upper metal lines, and second regions having a second distance between a lower surface of the first semiconductor substrate and an upper surface of second upper metal lines of the plurality of upper metal lines, the second distance being shorter than the first distance,
wherein the first upper metal lines and second upper metal lines are at the same height with respect to a top surface of the second semiconductor substrate, and
wherein the first regions and the second regions are alternately disposed in the third direction.

17. The memory device of claim 16 , wherein the first upper metal lines are configured to transmit a first signal, and the second upper metal lines are configured to transmit a second signal different from the first signal, and
the first signal includes a reference signal for operating the memory cell region and the peripheral circuit region.

18. The memory device of claim 16 , wherein the plurality of lower metal lines include first lower metal lines configured to transmit a first signal, and second lower metal lines configured to transmit a second signal different from the first signal, and
the first lower metal lines are disposed be

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sujeong
• Kim Inmo

Classifications

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/41

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title