Integrated circuit structure with through-metal through-substrate interconnect and method

Patent metadata

Field	Value
Publication number	US-12062574-B2
Application number	US-202117389779-A
Country	US
Kind code	B2
Filing date	Jul 30, 2021
Priority date	Jul 30, 2021
Publication date	Aug 13, 2024
Grant date	Aug 13, 2024

Abstract

Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

First claim

What is claimed is:

1. A structure comprising:
a substrate having a first side and a second side opposite the first side;
a first dielectric layer adjacent to the second side;
a metallic feature in a metallic feature opening extending through the first dielectric layer;
a second dielectric layer on the metallic feature and the first dielectric layer;
an interconnect in an interconnect opening,
wherein the interconnect opening includes a lower portion extending from the first side of the substrate to the metallic feature, a middle portion extending from the lower portion through the metallic feature, and an upper portion extending from the middle portion through the second dielectric layer to a top surface of the second dielectric layer,
wherein a top of the interconnect is co-planar with the top surface of the second dielectric layer,
wherein the interconnect includes a conductive fill material within the interconnect opening extending continuously through the lower portion, the middle portion, and the upper portion, and
wherein, within the middle portion of the interconnect opening, the interconnect is in direct contact with and electrically connected to the metallic feature; and

an additional metallic feature, wherein a bottom surface of the additional metallic feature is in contact with the top of the interconnect and extends onto the top surface of the second dielectric layer.

2. The structure of claim 1 , wherein the structure further comprises a metallic film on the first side of the substrate immediately adjacent to the interconnect.

3. The structure of claim 1 , wherein the upper portion is wider than the middle portion.

4. The structure of claim 1 , further comprising: an insulator layer in the lower portion of the interconnect opening and electrically isolating the interconnect from the substrate.

5. The structure of claim 1 , further comprising an additional interconnect, wherein the additional interconnect is physically separated from any adjacent interconnects, is within an additional interconnect opening that extends from the first side of the substrate through the metallic feature and further through the second dielectric layer, and is in direct contact with and electrically connected to the metallic feature.

6. The structure of claim 1 , wherein the interconnect further comprises at least one of an adhesive layer and a barrier layer lining sidewalls of the interconnect opening and the conductive fill material filling remaining space within the interconnect opening.

7. A structure comprising:
a multi-layered substrate having a first side and a second side opposite the first side, wherein the multi-layered substrate comprises: a channel layer; and a barrier layer on the channel layer;
a first dielectric layer on the barrier layer;
a transistor comprising:
metallic source/drain regions in source/drain openings, respectively, wherein the source/drain openings extend from a top surface of the first dielectric layer to the channel layer and wherein the metallic source/drain regions are immediately adjacent to the channel layer; and
a gate structure in a gate opening, wherein the gate opening is positioned laterally between the source/drain openings and extends from the top surface of the first dielectric layer to a bottom surface of the first dielectric layer;

a second dielectric layer on the first dielectric layer, the metallic source/drain regions, and the gate structure;
at least one contact extending vertically from the transistor to a top surface of the second dielectric layer;
an interconnect in an interconnect opening,
wherein the interconnect opening includes a lower portion extending from the first side of the multi-layer substrate to one metallic source/drain region of the metallic source/drain regions, a middle portion extending from the lower portion through the one metallic source/drain region, and an upper portion extending from the middle portion through the second dielectric layer to the top surface of the second dielectric layer,
wherein top surfaces of the contact and the interconnect are co-planar with the top surface of the second dielectric layer,
wherein the interconnect includes a conductive fill material within the interconnect opening extending continuously from the first side of the multi-layer substrate through the lower portion, the middle portion, and the upper portion, and
wherein, within the middle portion of the interconnect opening, the interconnect is in direct contact with and electrically connected to the one metallic source/drain region; and

an additional metallic feature, wherein a bottom surface of the additional metallic feature is in contact with a top surface of the interconnect and extends onto the top surface of the second dielectric layer.

8. The structure of claim 7 , further comprising a metallic film on the first side of the multi-layered substrate immediately adjacent to the interconnect.

9. The structure of claim 7 , wherein the upper portion is wider than the middle portion.

10. The structure of claim 7 , wherein the gate structure comprises a gate conductor layer in the gate opening immediately adjacent to the barrier layer.

11. The structure of claim 7 ,
wherein the transistor comprises a metal-insulator-semiconductor high electron mobility transistor, and
wherein the gate structure comprises: a gate dielectric layer immediately adjacent to the barrier layer and a gate conductor layer on the gate dielectric layer.

12. The structure of claim 7 ,
wherein the multi-layered substrate further comprises: an initial semiconductor substrate layer; a buffer layer on the initial semiconductor substrate layer; and the channel layer on the buffer layer,
wherein the buffer layer, the channel layer, and the barrier layer comprise epitaxial semiconductor layers on the initial semiconductor substrate layer,
wherein the interconnect further includes at least one of an adhesive layer and a barrier layer lining sidewalls of the interconnect opening and the conductive fill material filling remaining space within the interconnect opening, and
wherein the structure further comprises: an insulator layer in the lower portion of the interconnect opening electrically isolating the interconnect from the initial semiconductor substrate layer, from the buffer layer, and from the channel layer.

13. The structure of claim 7 , further comprising: an additional interconnect, wherein the additional interconnect is physically separated from any adjacent interconnects, is within an additional interconnect opening that extends from the first side of the multi-layer substrate through the one metallic source/drain region and further through the second dielectric layer, and includes the conductive fill material extending continuously from the first side of the multi-layered substrate through the second dielectric layer.

14. The structure of claim 7 , wherein the metallic source/drain regions include two metallic source/drain regions including: a metallic source region and a metallic drain region, and wherein the metallic source region has a larger surface area than the metallic drain region and is closer to the gate structure than the metallic drain region.

15. The structure of claim 8 , wherein the conductive fill material is different from metallic materials of the metallic film and the additional metallic feature.

16. The structure of claim 8 , wherein the conductive fill material is tungsten.

17. A structure comprising:
a multi-layered substrate having a first side and a second side opposite the first side, wherein

Assignees

• Globalfoundries Us Inc

Inventors

• He Zhong-Xiang
• Rassel Richard J
• Joseph Alvin J
• Hazbun Ramsey M
• Hwang Jeonghyun
• Levy Mark D

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/427

  Power or ground buses · CPC title