Silicon carbide semiconductor device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-12057498-B2
Application number	US-202117410044-A
Country	US
Kind code	B2
Filing date	Aug 24, 2021
Priority date	Feb 27, 2019
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

A semiconductor device includes a semiconductor element having a substrate, a drift layer, a base region, a source region, trench gate structures, an interlayer insulating film, a source electrode, and a drain electrode. The substrate is made of silicon carbide. The drift layer is disposed on the substrate and has an impurity concentration lower than the substrate. The base region is made of silicon carbide and disposed on the drift layer. The source region is made of silicon carbide having an impurity concentration higher than the drift layer. Each trench gate structure has a gate trench, a gate insulating film, and a gate electrode. The interlayer insulating film covers the gate electrode and the gate insulating film. The source electrode is in ohmic-contact with the source region. The drain electrode is disposed on a rear surface of the substrate.

First claim

What is claimed is:

1. A silicon carbide semiconductor device comprising:
an inverted semiconductor element including:
a substrate made of silicon carbide having a first conductivity type or a second conductivity type;
a drift layer disposed on the substrate and made of silicon carbide having the first conductivity type with an impurity concentration lower than the substrate;
a base region made of silicon carbide having the second conductivity type and disposed on the drift layer;
a source region made of silicon carbide having the first conductivity type with a first conductivity type impurity concentration higher than the drift layer and disposed on the base region;
a plurality of trench gate structures each of which has a gate trench, a gate insulating film and a gate electrode, the gate trench disposed deeper than the base region from a surface of the source region, the gate insulating film covering an inner wall of the gate trench, the gate electrode disposed on the gate insulating film, the trench gate structures aligned in a stripe shape along a single direction corresponding to a longitudinal direction;
an interlayer insulating film covering the gate electrode and the gate insulating film, and having a contact hole;
a source electrode in ohmic-contact with the source region through the contact hole; and
a drain electrode disposed at a rear surface of the substrate,
wherein the source region includes:
a first source region that has an epitaxial growth layer disposed at the base region; and
a second source region that is in contact with the source electrode, and that has an ion implanted layer having the first conductivity type with the first conductivity type impurity concentration higher than the first source region, wherein

the first source region is in contact with the base region,
the first source region has a thickness of 0.2 μm to 0.5 μm and an impurity concentration of 2.0×10 16 to 1.0×10 17 /cm 3 , and
the second source region has a thickness of 0.1 μm to 0.2 μm and a second conductivity type impurity concentration of 1.0×10 18 to 5.0×10 19 /cm 3 .

2. The silicon carbide semiconductor device according to claim 1 ,
wherein the gate trench is rounded and tilted at a portion corresponding to the second source region.

3. A silicon carbide semiconductor device comprising:
an inverted semiconductor element including:
a substrate made of silicon carbide having a first conductivity type or a second conductivity type;
a drift layer disposed on the substrate and made of silicon carbide having the first conductivity type with an impurity concentration lower than the substrate;
a base region made of silicon carbide having the second conductivity type and disposed on the drift layer;
a source region made of silicon carbide having the first conductivity type with a first conductivity type impurity concentration higher than the drift layer and disposed on the base region;
a plurality of trench gate structures each of which has a gate trench, a gate insulating film and a gate electrode, the gate trench disposed deeper than the base region from a surface of the source region, the gate insulating film covering an inner wall of the gate trench, the gate electrode disposed on the gate insulating film, the trench gate structures aligned in a stripe shape along a single direction corresponding to a longitudinal direction;
an interlayer insulating film covering the gate electrode and the gate insulating film, and having a contact hole;
a source electrode in ohmic-contact with the source region through the contact hole; and
a drain electrode disposed at a rear surface of the substrate,
wherein the source region includes:
a first source region that has an epitaxial growth layer disposed at the base region; and
a second source region that is in contact with the source electrode, and that has an ion implanted layer having the first conductivity type with the first conductivity type impurity concentration higher than the first source region, and

wherein a non-doped layer is disposed between the base region and the source region, and has a carrier concentration of 1.0×10 16 /cm 3 and a thickness of 0.05 μm to 0.2 μm.

4. The silicon carbide semiconductor device according to claim 3 ,
wherein the first source region has a thickness of 0.2 μm to 0.5 μm and an impurity concentration of 2.0×10 16 to 1.0×10 17 /cm 3 , and
wherein the second source region has a thickness of 0.1 μm to 0.2 μm and a second conductivity type impurity concentration of 1.0×10 18 to 5.0×10 19 /cm 3 .

5. The silicon carbide semiconductor device according to claim 3 ,
wherein the gate trench is rounded and tilted at a portion corresponding to the second source region.

6. A method for manufacturing a silicon carbide semiconductor device including an inverted semiconductor element, the method comprising:
preparing a substrate made of silicon carbide having a first conductivity type or a second conductivity type;
forming a drift layer disposed on the substrate and made of silicon carbide having the first conductivity type with an impurity concentration lower than the substrate;
forming a base region made of silicon carbide having the second conductivity type on the drift layer;
forming a source region made of silicon carbide having the first conductivity type with a first conductivity type impurity concentration higher than the drift layer on the base region, the source region having
a first source region arranged at the base region, and
a second source region arranged on the first source region and having an impurity concentration higher than the first source region;
forming a plurality of trench gate structures by
forming a plurality of gate trenches deeper than the base region from a surface of the source region and aligned in a stripe shape along a single direction corresponding to a longitudinal direction,
forming a gate insulating film at an inner surface of each of the gate trenches, and
forming a gate electrode on the gate insulating film;
forming a source electrode electrically connected to the base region; and
forming a drain electrode at a rear surface of the substrate,
wherein, in the forming of the base region, the base region is formed by epitaxial growth, and
wherein, in the forming of the source region, the first source region is formed by the epitaxial growth at a surface of the base region to have a thickness of 0.2 μm to 0.5 μm and an impurity concentration of 2.0×10 16 to 1.0×10 17 /cm 3 , and then the second source region is formed by ion implantation of first conductivity type impurities to the first source region to have a thickness of 0.1 μm to 0.2 μm and a second conductivity type impurity concentration of 1.0×10 18 to 5.0×10 19 /cm 3 .

7. A method for manufacturing a silicon carbide semiconductor including an inverted semiconductor element, the method comprising:
preparing a substrate made of silicon carbide having a first conductivity type or a second conductivity type;
forming a drift layer disposed on the substrate and made of silicon carbide having the first conductivity type with an impurity concentration lower than the substrate;
forming a base region made of silicon carbide having the second conductivity type on the drift layer;
forming a non-doped layer having a carrier concentration of 1.0×10 16 /cm 3 and a thickness of 0.05 μm to 0.2 μm on the base region;
forming a source region made of silicon carbide having the first conductivity type with a first conductivity type impurity concentration higher than the drift layer on the non-doped region, the source region having
a first source region arranged at the base region, and
a second source region arranged on the first source region and having an impurity concen

Assignees

• Denso Corp

Inventors

• Takeuchi Yuichi
• Suzuki Katsumi
• Yamashita Yusuke
• Kato Takehiro

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P70/20

  Cleaning during device manufacture · CPC title

• H10P30/2042

  into crystalline silicon carbide · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/3442

  N-type · CPC title