EM and RF mitigation silicon structures in stacked die microprocessors for die to platform and die-die RF noise suppression

Patent metadata

Field	Value
Publication number	US-12057433-B2
Application number	US-202016910014-A
Country	US
Kind code	B2
Filing date	Jun 23, 2020
Priority date	Jun 23, 2020
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

Embodiments disclosed herein include electronic packages and their components. In an embodiment, an electronic package comprises a package substrate and a base die over the package substrate. In an embodiment, the electronic package further comprises a plurality of chiplets over the base die. In an embodiment, the base die comprises a substrate, a first metal layer and a second metal layer between the substrate and the plurality of chiplets, and a third metal layer and a fourth metal layer between the package substrate and the substrate. In an embodiment, a filter is integrated into one or more layers of the base die.

First claim

What is claimed is:

1. An electronic package, comprising:
a package substrate;
a base die over the package substrate; and
a plurality of chiplets over the base die, wherein the base die comprises:
a substrate;
a first metal layer and a second metal layer between the substrate and the plurality of chiplets;
a third metal layer and a fourth metal layer between the package substrate and the substrate, the third metal layer vertically spaced apart from the fourth metal layer; and
a filter integrated into one or more layers of the base die.

2. The electronic package of claim 1 , wherein the filter is a common mode choke.

3. The electronic package of claim 2 , wherein the common mode choke comprises:
a first capacitor having a first plate and a second plate;
a second capacitor having a third plate and a fourth plate;
a first spiral trace connected between the first plate and the third plate;
a second spiral trace connected between the second plate and the fourth plate.

4. The electronic package of claim 3 , wherein the first capacitor and the second capacitor are between the first metal layer and the second metal layer, and wherein the first spiral trace and the second spiral trace are in the second metal layer.

5. The electronic package of claim 3 , wherein the first capacitor and the second capacitor are between the first metal layer and the second metal layer, wherein the first spiral trace is in the third metal layer, and wherein the second spiral trace is in the fourth metal layer.

6. The electronic package of claim 5 , wherein through substrate vias connect the first spiral trace and the second spiral trace to the first capacitor and the second capacitor.

7. The electronic package of claim 2 , wherein the common mode choke comprises a first inductor and a second inductor.

8. The electronic package of claim 7 , wherein the first inductor comprises a spiral trace in the first metal layer, and wherein the second inductor comprises a spiral trace in the second metal layer.

9. The electronic package of claim 7 , wherein the first inductor comprises a first through substrate via, and wherein the second inductor comprises a second through substrate via.

10. The electronic package of claim 1 , wherein the filter comprises a notch filter with an inductor and a capacitor connected in series.

11. The electronic package of claim 10 , wherein the inductor comprises a spiral trace in the first metal layer, and wherein the capacitor comprises parallel plates between the first metal layer and the second metal layer.

12. The electronic package of claim 10 , wherein the inductor comprises a pair of through silicon vias connected together by a trace in the third metal layer, and wherein the capacitor comprises parallel plates between the first metal layer and the second metal layer.

13. The electronic package of claim 10 , wherein the inductor comprises a conductive spiral disposed in both the first metal layer and the second metal layer, and wherein the capacitor comprises a floating pad in the second metal layer.

14. The electronic package of claim 10 , wherein the inductor comprises a trace in the first metal layer, and wherein the capacitor comprises a floating pad in the second metal layer.

15. An electronic package, comprising:
a package substrate;
a base die over the package substrate; and
a plurality of chiplets over the base die, wherein the base die comprises:
a substrate;
a first metal layer and a second metal layer between the substrate and the plurality of chiplets;
a third metal layer and a fourth metal layer between the package substrate and the substrate; and
a filter integrated into one or more layers of the base die, wherein the filter is a common mode choke, and wherein the common mode choke comprises:

a first capacitor having a first plate and a second plate;
a second capacitor having a third plate and a fourth plate;
a first spiral trace connected between the first plate and the third plate; and
a second spiral trace connected between the second plate and the fourth plate.

16. The electronic package of claim 15 , wherein the first capacitor and the second capacitor are between the first metal layer and the second metal layer, and wherein the first spiral trace and the second spiral trace are in the second metal layer.

17. The electronic package of claim 15 , wherein the first capacitor and the second capacitor are between the first metal layer and the second metal layer, wherein the first spiral trace is in the third metal layer, and wherein the second spiral trace is in the fourth metal layer.

18. The electronic package of claim 17 , wherein through substrate vias connect the first spiral trace and the second spiral trace to the first capacitor and the second capacitor.

19. An electronic package, comprising:
a package substrate;
a base die over the package substrate; and
a plurality of chiplets over the base die, wherein the base die comprises:
a substrate;
a first metal layer and a second metal layer between the substrate and the plurality of chiplets;
a third metal layer and a fourth metal layer between the package substrate and the substrate; and
a filter integrated into one or more layers of the base die, wherein the filter is a common mode choke, wherein the common mode choke comprises a first inductor and a second inductor, and wherein:

the first inductor comprises a spiral trace in the first metal layer, and the second inductor comprises a spiral trace in the second metal layer; or
the first inductor comprises a first through substrate via, and wherein the second inductor comprises a second through substrate via.

20. The electronic package of claim 19 , wherein the first inductor comprises the spiral trace in the first metal layer, and wherein the second inductor comprises the spiral trace in the second metal layer.

21. The electronic package of claim 19 , wherein the first inductor comprises the first through substrate via, and wherein the second inductor comprises the second through substrate via.

22. An electronic package, comprising:
a package substrate;
a base die over the package substrate; and
a plurality of chiplets over the base die, wherein the base die comprises:
a substrate;
a first metal layer and a second metal layer between the substrate and the plurality of chiplets;
a third metal layer and a fourth metal layer between the package substrate and the substrate; and
a filter integrated into one or more layers of the base die, wherein the filter comprises a notch filter with an inductor and a capacitor connected in series, and wherein:

the inductor comprises a spiral trace in the first metal layer, and wherein the capacitor comprises parallel plates between the first metal layer and the second metal layer; or
the inductor comprises a pair of through silicon vias connected together by a trace in the third metal layer, and wherein the capacitor comprises parallel plates between the first metal layer and the second metal layer; or
the inductor comprises a conductive spiral disposed in both the first metal layer and the second metal layer, and wherein the capacitor comprises a floating pad in the second metal layer; or
the inductor comprises a trace in the first metal layer, and wherein the capacitor comprises a floating pad in the second metal layer.

23. The electronic package of claim 22 , wherein the inductor comprises the spiral trace in the first metal layer, and wherein

Assignees

• Intel Corp

Inventors

• Shekhar Sameer
• Jain Amit

Classifications

• H10W42/267

  Patterned shielding planes · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W42/271

  the arrangements being between stacked chips · CPC title