Embedded three-dimensional electrode capacitor

Patent metadata

Field	Value
Publication number	US-12057386-B2
Application number	US-202017024507-A
Country	US
Kind code	B2
Filing date	Sep 17, 2020
Priority date	Sep 17, 2020
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

Embedded three-dimensional electrode capacitors, and methods of fabricating three-dimensional electrode capacitors, are described. In an example, an integrated circuit structure includes a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern. An insulator structure is on the first conductive structure of the first metallization layer. A second metallization layer is above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, and the second conductive structure having the honeycomb pattern.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern, and the first conductive structure having an uppermost surface;
an insulator structure on the first conductive structure of the first metallization layer; and
a second metallization layer above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, the second conductive structure having the honeycomb pattern, and the second conductive structure having a bottommost surface above the uppermost surface of the first conductive structure.

2. The integrated circuit structure of claim 1 , wherein the insulator structure is in the second dielectric layer.

3. The integrated circuit structure of claim 1 , wherein the insulator structure comprises a layer of silicon nitride.

4. The integrated circuit structure of claim 3 , wherein the insulator structure further comprises a first layer of titanium nitride above and on the layer of silicon nitride.

5. The integrated circuit structure of claim 4 , wherein the insulator structure further comprises a second layer of titanium nitride below the layer of silicon nitride, the layer of silicon nitride on the second layer of titanium nitride.

6. The integrated circuit structure of claim 1 , wherein the first and second conductive structures comprise tungsten.

7. The integrated circuit structure of claim 1 , wherein the first and second conductive structures comprise copper.

8. An apparatus, comprising:
a capacitor comprising:
a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern, and the first conductive structure having an uppermost surface;
an insulator structure on the first conductive structure of the first metallization layer; and
a second metallization layer above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, the second conductive structure having the honeycomb pattern, and the second conductive structure having a bottommost surface above the uppermost surface of the first conductive structure; and

an active component in the first dielectric layer, the active component electrically coupled to the second conductive structure.

9. The apparatus of claim 8 , wherein the active component is an optical device.

10. The apparatus of claim 8 , wherein the insulator structure is in the second dielectric layer.

11. The apparatus of claim 8 , wherein the insulator structure comprises a layer of silicon nitride.

12. The apparatus of claim 11 , wherein the insulator structure further comprises a first layer of titanium nitride above and on the layer of silicon nitride.

13. The apparatus of claim 12 , wherein the insulator structure further comprises a second layer of titanium nitride below the layer of silicon nitride, the layer of silicon nitride on the second layer of titanium nitride.

14. The apparatus of claim 8 , wherein the first and second conductive structures comprise tungsten.

15. The apparatus of claim 8 , wherein the first and second conductive structures comprise copper.

16. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern, and the first conductive structure having an uppermost surface;
an insulator structure on the first conductive structure of the first metallization layer; and
a second metallization layer above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, the second conductive structure having the honeycomb pattern, and the second conductive structure having a bottommost surface above the uppermost surface of the first conductive structure.

17. The computing device of claim 16 , further comprising:
a memory coupled to the board.

18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.

19. The computing device of claim 16 , further comprising:
a camera coupled to the board.

20. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

Assignees

• Intel Corp

Inventors

• Qian Wei
• Tran Cung
• Park Sungbong
• Heck John
• Isenberger Mark
• Slavin Seth
• Huang mengyuan
• Magruder Kelly
• Frish Harel
• Defrees Reece
• Li Zhi

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10D1/692

  Electrodes · CPC title

• H01L23/528

  Electricity · mapped topic

• H01L23/5223 Primary

  Electricity · mapped topic