Display apparatus

Patent metadata

Field	Value
Publication number	US-12057066-B2
Application number	US-202217581975-A
Country	US
Kind code	B2
Filing date	Jan 23, 2022
Priority date	May 12, 2021
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

A display apparatus that prevents visual recognition of flickering in each of display areas having different resolutions includes a first pixel circuit, a first display element, a second pixel circuit, and a second display element. The first pixel circuit includes: a first driving transistor configured to control a first current that flows to the first display element; and a first initializing transistor configured to apply a first initializing voltage to a gate of the first driving transistor in response to a first scan signal. The second pixel circuit includes: a second driving transistor configured to control a second current that flows to the second display element; and a second initializing transistor configured to apply a second initializing voltage having a level different from a level of the first initializing voltage to a gate of the second driving transistor in response to the first scan signal.

First claim

What is claimed is:

1. A display apparatus comprising:
a first pixel circuit;
a first display element connected to the first pixel circuit;
a second pixel circuit; and
a second display element connected to the second pixel circuit;
a substrate in which a first area and a second area are defined, the second area being at least partially surrounded by the first area;
a first voltage line at least partially overlapping the first area and configured to transmit a first initializing voltage to the first pixel circuit; and
a second voltage line at least partially overlapping the first area and the second area and configured to transmit a second initializing voltage to the second pixel circuit,
wherein the first pixel circuit comprises:
a first driving transistor configured to control a first current that flows to the first display element; and
a first initializing transistor configured to apply the first initializing voltage to a gate of the first driving transistor in response to a first scan signal, and

the second pixel circuit comprises:
a second driving transistor configured to control a second current that flows to the second display element; and
a second initializing transistor configured to apply the second initializing voltage having a level different from a level of the first initializing voltage to a gate of the second driving transistor in response to the first scan signal,

wherein the first voltage line extends in a row direction and has a first portion and a second portion physically spaced apart from each other by the second area.

2. The display apparatus of claim 1 , wherein a level of the first initializing voltage is higher than a level of the second initializing voltage.

3. The display apparatus of claim 1 , wherein the first pixel circuit further comprises a third initializing transistor configured to apply a third initializing voltage to an anode of the first display element in response to a second scan signal, and
the second pixel circuit further comprises a fourth initializing transistor configured to apply a fourth initializing voltage to an anode of the second display element in response to the second scan signal.

4. The display apparatus of claim 3 , wherein a level of the third initializing voltage is higher than a level of the fourth initializing voltage.

5. The display apparatus of claim 3 , wherein the first pixel circuit further comprises:
a first scan transistor configured to transmit a first data voltage to the first driving transistor in response to a third scan signal;
a first storage capacitor having a first electrode and a second electrode, the second electrode being connected to the gate of the first driving transistor; and
a first compensating transistor configured to connect a drain of the first driving transistor to the gate of the first driving transistor in response to a fourth scan signal, and
the second pixel circuit further comprises:
a second scan transistor configured to transmit a second data voltage to the second driving transistor in response to the third scan signal;
a second storage capacitor having a third electrode and a fourth electrode, the fourth electrode being connected to the gate of the second driving transistor; and
a second compensating transistor configured to connect a drain of the second driving transistor to the gate of the second driving transistor in response to the fourth scan signal.

6. The display apparatus of claim 5 , wherein conductivity types of the first compensating transistor and the second compensating transistor are opposite to conductivity types of the first scan transistor and the second scan transistor, and are identical to conductivity types of the first initializing transistor and the second initializing transistor.

7. The display apparatus of claim 5 , wherein the third scan signal and the fourth scan signal are substantially synchronized with each other.

8. The display apparatus of claim 1 , wherein conductivity types of the first initializing transistor and the second initializing transistor are the same as each other and are opposite to conductivity types of the first driving transistor and the second driving transistor which are the same as each other.

9. The display apparatus of claim 1 , wherein an emission area of the second display element is greater than an emission area of the first display element.

10. The display apparatus of claim 1 , wherein the first display element and the second display element are each provided in plurality, and
a number of first display elements per unit area is greater than a number of second display elements per unit area.

11. The display apparatus of claim 1 , wherein the second voltage line includes: a first portion surrounding at least a portion of the second area; and a second portion connected to the first portion and extending in a row direction,
the first portion of the second voltage line overlaps the first area, and
the second portion of the second voltage line overlaps the second area.

12. The display apparatus of claim 1 , further comprising:
a third pixel circuit; and
a third display element connected to the third pixel circuit,
wherein the third pixel circuit comprises:
a third driving transistor configured to control a third current that flows to the third display element; and
a third initializing transistor configured to apply the second initializing voltage to a gate of the third driving transistor in response to the first scan signal, and

wherein in a plan view, the second pixel circuit and the second display element are spaced apart from each other, and the third pixel circuit and the third display element at least partially overlap each other.

13. The display apparatus of claim 12 ,
wherein the second area comprises a component area and a middle area, the middle area being located between the first area and the component area,
the first pixel circuit and the first display element are arranged on the first area,
the second display element is arranged on the component area of the second area, and
the second pixel circuit, the third pixel circuit, and the third display element are arranged on the middle area of the second area.

14. The display apparatus of claim 12 , wherein the first pixel circuit further comprises a fourth initializing transistor configured to apply a third initializing voltage to an anode of the first display element in response to a second scan signal,
the second pixel circuit further comprises a fifth initializing transistor configured to apply a fourth initializing voltage to an anode of the second display element in response to the second scan signal, and
the third pixel circuit further comprises a sixth initializing transistor configured to apply the fourth initializing voltage to an anode of the third display element in response to the second scan signal.

15. The display apparatus of claim 14 , wherein a level of the third initializing voltage is higher than a level of the fourth initializing voltage.

16. The display apparatus of claim 12 , wherein an emission area of
the third display element is equal to an emission area of the second display element, and
the emission area of the third display element is greater than an emission area of the first display element.

17. The display apparatus of claim 12 , wherein the first display element, the second display element, and the third display element are each provided in plurality, and
a number of second display elements per unit area is equal to the number of third display elements per unit area, and
a number

Assignees

• Samsung Display Co Ltd

Inventors

• An Jinsung
• Kim Sungho
• Seong Seokje
• Woo Minwoo
• Lee Wangwoo
• Lee Jiseon

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/8731

  multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title