Thin film transistor substrate

Patent metadata

Field	Value
Publication number	US-2016125809-A1
Application number	US-201514682451-A
Country	US
Kind code	A1
Filing date	Apr 9, 2015
Priority date	Oct 29, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

A thin film transistor (TFT) substrate and a display apparatus including the same. The TFT substrate includes a plurality of first pixels that are disposed on a first pixel row, a plurality of second pixels that are disposed on a second pixel row adjacent to the first pixel row, a plurality of third pixels that are disposed on a third pixel row adjacent to the second pixel row, a first initialization voltage line that is disposed between the first pixel row and the second pixel row, and applies a first initialization voltage to the plurality of first pixels and the plurality of second pixels, and a second initialization voltage line that is disposed between the second pixel row and the third pixel row, and applies a second initialization voltage, having a level which differs from a level of the first initialization voltage, to the plurality of second pixels and the plurality of third pixels.

First claim

What is claimed is:

1 . A thin film transistor (TFT) substrate comprising:
a plurality of first pixels that are disposed on a first pixel row; a plurality of second pixels that are disposed on a second pixel row adjacent to the first pixel row; a plurality of third pixels that are disposed on a third pixel row adjacent to the second pixel row; a first initialization voltage line that is disposed between the first pixel row and the second pixel row, the first initialization voltage line being configured to apply a first initialization voltage to the plurality of first pixels and the plurality of second pixels; and a second initialization voltage line that is disposed between the second pixel row and the third pixel row, the second initialization voltage line being configured to apply a second initialization voltage, having a level which differs from a level of the first initialization voltage, to the plurality of second pixels and the plurality of third pixels, wherein the first pixels of the first pixel row, the second pixels of the second pixel row, and the third pixels of the third pixel row are aligned to form a plurality of pixel columns.

2 . The TFT substrate of claim 1 , wherein a first pixel and a second pixel of a same pixel column are symmetrical about the first initialization voltage line.

3 . The TFT substrate of claim 1 , wherein a second pixel and a third pixel of a same pixel column are symmetrical about the second initialization voltage line.

4 . The TFT substrate of claim 1 , further comprising a first connection electrode that electrically connects the first initialization voltage line to a pair of first pixels and a pair of second pixels disposed on two adjacent pixel columns.

5 . The TFT substrate of claim 4 , further comprising:
a first active layer connection line connected to an initialization TFT of each of the pair of first pixels and the pair of second pixels disposed on the two adjacent pixel columns; a first insulating layer formed between the first active layer connection line and the first connection electrode, and including a first common contact hole; and a second insulating layer and a third insulating layer sequentially formed on the first connection electrode, and each including a first via hole, wherein, the initialization TFT transfers the first initialization voltage, the first connection electrode contacts the first active layer connection line through the first common contact hole, and the first initialization voltage line is formed on the third insulating layer, and contacts the first connection electrode through the first via hole.

6 . The TFT substrate of claim 1 , further comprising a second connection electrode that electrically connects the second initialization voltage line to a pair of second pixels and a pair of third pixels disposed on two adjacent pixel columns.

7 . The TFT substrate of claim 6 , further comprising:
a second active layer connection line connected to a bypass TFT of each of the pair of second pixels and the pair of third pixels disposed on the two adjacent pixel columns; a first insulating layer formed between the second active layer connection line and the second connection electrode, and including a second common contact hole; and a second insulating layer and a third insulating layer sequentially formed on the second connection electrode, and each including a second via hole, wherein, the bypass TFT transfers the second initialization voltage, the second connection electrode contacts the second active layer connection line through the second common contact hole, and the second initialization voltage line is formed on the third insulating layer, and contacts the second connection electrode through the second via hole.

8 . The TFT substrate of claim 1 , further comprising:
a plurality of first scan lines and a plurality of second scan lines that are disposed on each of the first to third pixel rows, and respectively apply a first scan signal and a second scan signal to the plurality of first pixels, the plurality of second pixels, and the plurality of third pixels; a plurality of data lines that intersect the plurality of first scan lines and the plurality of second scan lines, are disposed on each pixel column, and apply data signals to the plurality of first pixels, the plurality of second pixels, and the plurality of third pixels; and a plurality of driving voltage lines that intersect the plurality of first scan lines and the plurality of second scan lines, are disposed on each pixel column, and apply a first source voltage to the plurality of first pixels, the plurality of second pixels, and the plurality of third pixels.

9 . The TFT substrate of claim 8 , wherein the first scan line and second scan line of the first pixel row are symmetrical with the first scan line and second scan line of the second pixel row about the first initialization voltage line.

10 . The TFT substrate of claim 8 , wherein the first scan line and second scan line of the first pixel row are symmetrical with the first scan line and second scan line of the third pixel row about the second initialization voltage line.

11 . A thin film transistor (TFT) substrate including a plurality of pixels arranged in aligned pixel rows and pixel columns, each of the plurality of pixels comprising:
a driving TFT that outputs a driving current corresponding to a data signal to a light-emitting device in response to a first scan signal; an initialization TFT that transfers a first initialization voltage to a gate electrode of the driving TFT in response to a second scan signal; and a bypass TFT that transfers a second initialization voltage, having a level which differs from a level of the first initialization voltage, to an anode electrode of the light-emitting device in response to the second scan signal, wherein, each of the plurality of pixels is connected to a first initialization voltage line via which the first initialization voltage is supplied and a second initialization voltage line via which the second initialization voltage is supplied, the first initialization voltage line is connected to initialization TFTs of adjacent pixels of a same pixel row and pixels of a first pixel row adjacent thereto, and is disposed between the same pixel row and the first pixel row, and the second initialization voltage line is connected to bypass TFTs of adjacent pixels of the same pixel row and pixels of a second pixel row adjacent thereto, and is disposed between the same pixel row and the second pixel row.

12 . The TFT substrate of claim 11 , wherein each of the plurality of pixels of the same pixel row is symmetrical with a pixel of the first pixel row of a same pixel column about the first initialization voltage line.

13 . The TFT substrate of claim 11 , wherein each of the plurality of pixels of the same pixel row is symmetrical with a pixel of the second pixel row of a same pixel column about the second initialization voltage line.

14 . The TFT substrate of claim 11 , further comprising a first connection electrode that electrically connects the first initialization voltage line to a pair of pixels of the same pixel row disposed on two adjacent pixel columns and a pair of pixels of the first pixel row disposed on the two adjacent pixel columns.

15 . The TFT substrate of claim 11 , further comprising a second connection electrode that electrically connects the second initialization voltage line to a pair of pixels of the same pixel row disposed on two adjacent pixel columns and a pair of pixels of the second pixel row disposed o

Assignees

• Samsung Display Co Ltd

Inventors

• Hwang Wonmi

Classifications

• G09G2320/045

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• G09G2320/0242

  Compensation of deficiencies in the appearance of colours · CPC title

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G2310/0218

  with collection of electrodes in groups for n-dimensional addressing · CPC title

• G09G2310/0216

  Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines · CPC title