Memory comprising a matrix of resistive memory cells, and associated method of interfacing

Patent metadata

Field	Value
Publication number	US-12052876-B2
Application number	US-202117549162-A
Country	US
Kind code	B2
Filing date	Dec 13, 2021
Priority date	Dec 16, 2020
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

A memory includes a matrix of resistive memory cells and an interfacing device to interface the matrix, the interfacing device including at least a conversion capacitor, an electric source, a first switch and a second switch, the interfacing device being configured to: a) connect the conversion capacitor to the source by the second switch to charge the conversion capacitor, then, b) disconnect the conversion capacitor from the source and connect the conversion capacitor to the matrix to achieve a conversion between, on the one hand, a resistive state of one of the memory cells of the matrix, and, on the other hand, a state of charge of the conversion capacitor.

First claim

The invention claimed is:

1. A memory comprising:
a matrix of resistive memory cells with:
line electrical tracks,
column electrical tracks, and
resistive memory cells located at crossings between the line electrical tracks and the column electrical tracks, each memory cell being connected between one of the line electrical tracks and one of the column electrical tracks,

an interfacing device for interfacing said matrix, the interfacing device comprising at least one conversion capacitor, a voltage measuring device connected to terminals of the conversion capacitor, an electrical source, a first switch, a second switch and a control module, the interfacing device being configured to execute the following steps:
step a): connecting the conversion capacitor to the source by the second switch to charge the conversion capacitor,
after step a), step b) successively comprising:
disconnecting the conversion capacitor from the source, and connecting the conversion capacitor between one of the line electrical tracks and one of the column electrical tracks, by the first switch, to apply an electrical voltage to a cell to be read, said cell being located at a crossing of said line electrical track and said column electrical track,
acquiring a read result voltage, at the terminals of the conversion capacitor, by the voltage measuring device, and
determining a resistive state of said cell, by the control module, based on said read result voltage.

2. The memory according to claim 1 , wherein the interfacing device comprises an additional resistor connected in series with the conversion capacitor.

3. The memory according to claim 1 , wherein the conversion capacitor has a capacitance greater than a global parasitic capacitance, the global parasitic capacitance being representative of an effective electrical capacitance of the portion of the matrix corresponding to said line electrical track and to said column electrical track.

4. The memory according to claim 1 , wherein the control module is configured to control the first and second switches so as to execute steps a) and b).

5. The memory according to claim 4 , wherein the control module is further configured to:
in step a), control the second switch, or the source, so as to charge the conversion capacitor to a given initialisation voltage,
in step b), control the first and second switches so as to disconnect the source from the conversion capacitor, then to connect the conversion capacitor between said line electrical track and said column electrical track, during a predetermined memory cell reading time, before the acquisition of said read result voltage.

6. The memory according to claim 5 ,
wherein each memory cell comprises a memory element having at least one high resistive state and one low resistive state, as well as a selector arranged in series with the memory element, the selector being electrically conductive when a first voltage at its terminals is greater than a given threshold, and being electrically insulating otherwise,
and wherein, when a second voltage, applied at the terminals of the memory cell, is comprised between a low voltage threshold and a high voltage threshold:
if the memory element is in its low resistive state, then, the selector becomes electrically conductive and the memory cell then has a low memory resistance,
while if the memory element is in its high resistive state, then, the selector remains electrically insulating and the memory cell then has a high memory resistance.

7. The memory according to claim 6 , wherein said initialisation voltage is:
greater than said low voltage threshold, multiplied by a load balancing compensation coefficient, and
less than said high voltage threshold, multiplied by said coefficient,
the load balancing compensation coefficient being equal to the sum of the capacitance of the conversion capacitor and of a global parasitic capacitance, divided by the capacitance of the conversion capacitor, with the global parasitic capacitance being representative of the effective electrical capacitance of the portion of the matrix corresponding to said line electrical track and to said column electrical track.

8. The memory according to claim 7 , wherein the reading time is greater than: a high total effective resistance, multiplied by said global parasitic capacitance, the high total effective resistance being a total effective resistance in which the conversion capacitor discharges when it is connected to said line electrical track and to said column electrical track, the memory cell, located at the crossing of this line and of this column, having its high memory resistance.

9. The memory according to claim 6 ,
wherein the interfacing device comprises an additional resistor connected in series with the conversion capacitor,
wherein the selector is electrically conductive with the further condition that an electrical current that passes through the selector remains greater than a holding current,
and wherein the additional resistor is such that a low total effective resistance of the memory is less than said initialisation voltage divided by the holding current of the selector, the low total effective resistance being the total effective resistance in which the conversion capacitor discharges when it is connected to said line electrical track and to said column electrical track, the memory cell, located at the crossing of this line and of this column, having its low memory resistance.

10. The memory according to claim 9 , wherein the additional resistor is such that the low total effective resistance of the memory is, furthermore, less than said low voltage threshold divided by the holding current of the selector.

11. The memory according to claim 1 , wherein the conversion capacitor is located above or below the matrix of memory cells and extends parallel to the matrix, the matrix and the conversion capacitor being superimposed on each other.

12. A method for interfacing a memory in accordance with claim 1 , comprising the following steps:
step a): connecting the conversion capacitor to the source by the second switch to charge the conversion capacitor, then
step b):
disconnecting the conversion capacitor from the source, and connecting the conversion capacitor between one of the line electrical tracks and one of the column electrical tracks, by the first switch, then
acquiring a read result voltage, at the terminals of the conversion capacitor, by the voltage measuring device, then
determining a resistive state of said cell, by the control module, based on said read result voltage.

13. The method according to claim 12 , the memory comprising the voltage measuring device connected to the terminals of the conversion capacitor, wherein:
in step a), the second switch, or the source, is controlled so as to charge the conversion capacitor to a given initialisation voltage,
in step b), the first and second switches are controlled so as to disconnect the source from the conversion capacitor, then in such a way as to connect the conversion capacitor between said line electrical track and said column electrical track, during a predetermined memory cell reading time, before the acquisition of said read result voltage.

Assignees

• Commissariat Energie Atomique
• Weebit Nano Ltd

Inventors

• Verdy Anthonin
• Molas Gabriel
• Trotti Paola
• Regev Amir

Classifications

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/003 Primary

  Cell access · CPC title

• H10N70/821

  Device geometry · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title