Multi-level memory apparatus and data sensing method thereof

Patent metadata

Field	Value
Publication number	US-2016118115-A1
Application number	US-201514746200-A
Country	US
Kind code	A1
Filing date	Jun 22, 2015
Priority date	Oct 24, 2014
Publication date	Apr 28, 2016
Grant date	—

Abstract

A multi-level memory device may include a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current, a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage, a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal, and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal.

First claim

What is claimed is:

1 . A multi-level memory device comprising:
a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current; a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage; a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal; and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal.

2 . The multi-level memory device of claim 1 , wherein the current/voltage conversion circuit comprises:
a cell voltage charging circuit comprising a plurality of capacitors coupled in parallel, the plurality of capacitors including a capacitor that has a terminal, the capacitor being charged to have the cell voltage at the terminal; a path selection circuit configured to provide a path through which the copied cell current flows into the charged capacitor, in response to an output of the MSB determination circuit; and a comparison switching circuit configured to couple the charged capacitor to the LSB determination circuit and output the cell voltage according to the charging end signal.

3 . The multi-level memory device of claim 2 , wherein the plurality of capacitors have different capacitances.

4 . The multi-level memory device of claim 2 , wherein the plurality of capacitors have substantially the same capacitance.

5 . The multi-level memory device of claim 1 , wherein the charging time determination circuit comprises:
a section maximum cell current driving circuit configured to generate a section maximum cell current; a section maximum copied cell current driving circuit configured to generate a section maximum copied cell current that is substantially the same as the section maximum cell current; a section maximum cell voltage charging circuit including a terminal, the section maximum cell voltage charging circuit configured to receive the section maximum copied cell current and be charged to have a maximum charging voltage at the terminal; and a charging end signal generation circuit configured to output the charging end signal, when a level of the maximum charging voltage becomes substantially equal to that of a first reference voltage output from the LSB determination circuit.

6 . The multi-level memory device of claim 1 , wherein the LSB bit determination circuit comprises:
a reference voltage generation circuit configured to generate first and second reference voltages; a bit counter configured to output an LSB count signal according to the second reference voltage; a comparison circuit configured to compare the second reference voltage and the cell voltage and output a result of the comparison; and an LSB bit storage configured to store the LSB count signal and output the stored LSB count signal in response to the result of the comparison.

7 . A multi-level memory device comprising:
a plurality of analog/digital (A/D) converters; a charging time determination circuit configured to determine a time during which a copied cell current is converted into a cell voltage and output a charging end signal, the copied cell current being substantially the same as a cell current flowing through a memory cell; and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs of data stored in the memory cell according to the charging end signal, wherein the A/D converters share the charging time determination circuit and the LSB determination circuit.

8 . The multi-level memory device of claim 7 , wherein each of the A/D converters comprises:
a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing the cell current to a predetermined reference current; and a current/voltage conversion circuit configured to convert the copied cell current into the cell voltage.

9 . The multi-level memory device of claim 8 , wherein the current/voltage conversion circuit comprises:
a cell voltage charging circuit comprising a plurality of capacitors coupled in parallel, the plurality of capacitors including a capacitor that has a terminal, the capacitor being charged to have the cell voltage at the terminal; a path selection circuit configured to provide a path through which the copied cell current flows into the charged capacitor, in response to an output of the MSB determination circuit; and a comparison switching circuit configured to couple the charged capacitor to the LSB determination circuit and output the cell voltage according to the charging end signal.

10 . The multi-level memory device of claim 9 , wherein the plurality of capacitors have different capacitances.

11 . The multi-level memory device of claim 9 , wherein the plurality of capacitors have substantially the same capacitance.

12 . The multi-level memory device of claim 8 , wherein the charging time determination circuit comprises:
a section maximum cell current driving circuit configured to generate a section maximum cell current; a section maximum copied cell current driving circuit configured to generate a section maximum copied cell current that is substantially the same as the section maximum cell current; a section maximum cell voltage charging circuit including a terminal, the section maximum cell voltage charging circuit configured to receive the section maximum copied cell current and be charged to have a maximum charging voltage at the terminal; and a charging end signal generation circuit configured to output the charging end signal when the maximum charging voltage becomes substantially equal to that of a first reference voltage output from the LSB determination circuit.

13 . The multi-level memory device of claim 8 , wherein the LSB bit determination circuit comprises:
a reference voltage generation circuit configured to generate first and second reference voltages; a bit counter configured to output an LSB count signal according to the second reference voltage; a comparison circuit configured to compare the second reference voltage and the cell voltage and output a result of the comparison; and an LSB bit storage configured to store the LSB count signal and output the stored LSB count signal in response to the result of the comparison.

14 . A data sensing method of a multi-level memory device, comprising:
determining a plurality of most significant bits (MSBs) by comparing a cell current flowing through a memory cell to a predetermined reference current; converting a copied cell current obtained by coping the cell current into a cell voltage, and storing the cell voltage during a charging time; determining the charging time during which the copied cell current is converted into the cell voltage and outputting a charging end signal; and determining a plurality of least significant bits (LSBs) according to the cell voltage and the charging end signal.

15 . The data sensing method of claim 14 , wherein determining of the plurality of LSBs comprises:
sequentially coupling a plurality of capacitors to a power supply voltage; generating a reference voltage that increases in a stepwise manner as a number of the sequentially coupled capacitors increases; and outputting an LSB count signal when a level of the reference voltage becomes equal to or greater than that of th

Assignees

• Sk Hynix Inc
• Korea Advanced Inst Sci & Tech

Inventors

• Ryu Seung Tak
• Kwon Ji Wook
• Jin Dong Hwan

Classifications

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title