Recognizing transistor-transistor logic levels (TTL) at an input circuit with increased immunity to static current draw

Patent metadata

Field	Value
Publication number	US-12052016-B2
Application number	US-202117304621-A
Country	US
Kind code	B2
Filing date	Jun 23, 2021
Priority date	Jun 24, 2020
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

An input circuit that recognizes (e.g., buffers) logic level signals (e.g., of an input signal) represented by voltage levels that are lower than a supply voltage of an input circuit, and that exhibits static current draw immunity during stable states of an input signal. In one or more examples, series inverters are provided to buffer an input node and an output node of the input circuit. A voltage domain at the input circuit or output node may be higher than a voltage domain at the input node. Power supply to a first inverter of the series inverters may be turned OFF at least partially responsive to an indication that an output signal is a logic high; and power supply to the first inverter of the series inverters may be turned ON at least partially responsive to an indication that the output signal is a logic low. A third inverter may be maintained utilizing an input signal voltage to detect a falling edge of the input signal and turn ON power supply to the first inverter at least partially responsive thereto.

First claim

We claim:

1. A method, comprising:
providing series inverters to buffer an input node and an output node, wherein a voltage domain at the output node is higher than the voltage domain at the input node;
turning OFF power supply to a first inverter of the series inverters at least partially responsive to an indication that an output signal at the output node is a logic high; and
turning ON power supply to the first inverter of the series inverters with assistance of a third inverter at least partially responsive to an indication that the output signal is a logic low.

2. The method of claim 1 , comprising:
generating a voltage pulse via the third inverter to turn ON the power supply to the first inverter at least partially responsive to the input node exhibiting a decreasing voltage level that represents a falling edge of an input signal.

3. The method of claim 1 , comprising:
maintaining a second inverter of the series inverters when the power supply to the first inverter is turned OFF and when the power supply to the first inverter is turned ON.

4. The method of claim 1 , comprising:
enabling a reset switch to turn ON the power supply to the first inverter.

5. A method, comprising:
providing series inverters to buffer an input node and an output node, wherein a voltage domain at the output node is higher than the voltage domain at the input node;
turning OFF power supply to a first inverter of the series inverters at least partially responsive to an indication that an output signal is a logic high;
turning ON charging a sense capacitor at least partially responsive to the voltage at the input node and the voltage across the sense capacitor exhibiting different voltage levels;
supplying power to a third inverter via a voltage across the sense capacitor; and
generating a voltage pulse via the third inverter to turn ON power supply to the first inverter at least partially responsive to the input node exhibiting a decreasing voltage level that represents a falling edge of an input signal.

6. The method of claim 5 , comprising:
turning OFF charging the sense capacitor at least partially responsive to the voltage at the input node and the voltage across the sense capacitor exhibiting a same voltage level.

7. An apparatus, comprising:
series inverters selectively coupled to provide a buffer between an input node and an output node, wherein a voltage domain of the input node is different than a voltage domain of the series inverters;
a power switch arranged to:
turn OFF power supply to a first inverter of the series inverters at least partially responsive to an indication that an output signal at the output node is a logic high; and
turn ON power supply to the first inverter of the series inverters at least partially responsive to an indication that the output signal is a logic low; and

a third inverter to assist with power supply turn ON to the first inverter.

8. The apparatus of claim 7 , comprising:
a power supply and a supply lead of a second inverter of the series inverters coupled to supply power to the second inverter.

9. The apparatus of claim 8 , wherein the power supply and supply lead of the second inverter are coupled to maintain the second inverter both when the power supply to the first inverter is OFF and when the power supply to the first inverter is ON.

10. The apparatus of claim 7 , comprising:
the third inverter and a discharge switch coupled to turn ON the power switch at least partially responsive to the input node exhibiting a decreasing voltage level that represents a falling edge of an input signal.

11. An apparatus, comprising:
series inverters selectively coupled to provide a buffer between an input node and an output node, wherein a voltage domain of the input node is different than a voltage domain of the series inverters;
a power switch arranged to:
turn OFF power supply to a first inverter of the series inverters at least partially responsive to an indication that an output signal is a logic high; and
turn ON power supply to the first inverter of the series inverters at least partially responsive to an indication that the output signal is a logic low;

a third inverter and a discharge switch coupled to turn ON the power switch at least partially responsive to the input node exhibiting a decreasing voltage level that represents a falling edge of an input signal; and
a sense capacitor to store a voltage for maintaining a supply lead of the third inverter.

12. The apparatus of claim 11 , comprising:
a sense switch arranged to:
turn ON charging the sense capacitor at least partially responsive to the voltage at the input node and the voltage across the sense capacitor exhibiting a difference; and
turn OFF charging the sense capacitor at least partially responsive to the voltage at the input node and the voltage across the sense capacitor exhibiting a same voltage level.

13. The apparatus of claim 11 , wherein:
the third inverter arranged to generate a voltage pulse at least partially responsive to the input node exhibiting the decreasing voltage level that represents a falling edge of the input signal.

14. The apparatus of claim 13 , wherein:
a voltage level of the voltage pulse is substantially same as a voltage level utilized to represent a logic high for the input signal.

Assignees

• Microchip Tech Inc
• Microchip Tech Corporation

Inventors

• Devulapalli Sridhar
• Russell Daniel J
• Cherek Brian
• Klein Michael

Classifications

• H03K19/0013

  in field effect transistor circuits · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title