Fiber to chip coupler and method of making the same

Patent metadata

Field	Value
Publication number	US-12050348-B2
Application number	US-202318448032-A
Country	US
Kind code	B2
Filing date	Aug 10, 2023
Priority date	Aug 27, 2021
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

A method of making a chip includes depositing a first polysilicon layer on a top surface and a bottom surface of a substrate. The method further includes patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completed removed from the recess. The method further includes implanting dopants into the substrate to define an implant region. The method further includes depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region. The method further includes patterning the CESL to define a CESL block. The method further includes forming a waveguide and a grating in the substrate. The method further includes forming an interconnect structure over the waveguide, the grating and the CESL block. The method further includes etching the interconnect structure to define a cavity aligned with the grating.

First claim

What is claimed is:

1. A method of making a chip, the method comprising:
depositing a first polysilicon layer on a top surface and a bottom surface of a substrate;
patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completely removed from the recess;
implanting dopants into the substrate to define an implant region;
depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region;
patterning the CESL to define a CESL block;
forming a waveguide and a grating in the substrate;
forming an interconnect structure over the waveguide, the grating and the CESL block; and
etching the interconnect structure to define a cavity aligned with the grating.

2. The method of claim 1 , wherein patterning the CESL further comprises defining a CESL spacer parallel to a sidewall of the first polysilicon layer closest to the recess.

3. The method of claim 1 , further comprising:
depositing an oxide layer over the CESL block;
patterning the oxide layer to define an oxide spacer along a sidewall of the CESL block;
depositing a second polysilicon layer over the CESL block and the oxide spacer; and
patterning the second polysilicon layer to define a polysilicon spacer along a sidewall of the oxide spacer.

4. A method of making a chip, the method comprising:
forming a transistor in a substrate, wherein the transistor comprises a channel;
depositing an etch stop layer over the channel;
etching the etch stop layer to define an etch stop layer block;
forming a waveguide material on the substrate;
etching the waveguide material to define a grating;
depositing a polysilicon layer over the waveguide material;
forming an interconnect structure over the polysilicon layer and the etch stop layer block;
etching the interconnect structure over the polysilicon layer to define a cavity therein, wherein a cavity width of the cavity is different from a polysilicon width of the polysilicon layer.

5. The method of claim 4 , wherein etching the interconnect structure comprises defining the cavity having the cavity width greater than the polysilicon width.

6. The method of claim 4 , wherein etching the interconnect structure comprises defining the cavity having the cavity width less than the polysilicon width.

7. The method of claim 4 , wherein depositing the polysilicon layer comprises depositing a continuous polysilicon layer over the waveguide material.

8. The method of claim 4 , wherein depositing the polysilicon layer comprises depositing a discontinuous polysilicon layer over the waveguide material.

9. The method of claim 4 , further comprising depositing an oxide layer over the polysilicon layer, wherein the interconnect structure is formed over the oxide layer.

10. The method of claim 9 , further comprising extending the cavity through the oxide layer, wherein the cavity exposes the polysilicon layer.

11. The method of claim 9 , further comprising extending the cavity through the oxide layer and through the polysilicon layer, wherein a portion of the polysilicon layer remains under the oxide layer at a periphery of the waveguide material.

12. The method of claim 9 , further comprising extending the cavity through the oxide layer and through the polysilicon layer, wherein the polysilicon layer under the oxide layer is entirely removed.

13. The method of claim 12 , wherein removing the entirety of the polysilicon layer comprises defining an overhang for the oxide layer.

14. The method of claim 4 , wherein etching the interconnect structure comprises defining the cavity extending through less than an entire thickness of the interconnect structure.

15. A method of making a chip, the method comprising:
forming a waveguide material on a substrate;
etching the waveguide material to define a grating;
depositing a polysilicon layer over the grating;
depositing an oxide layer over the polysilicon layer;
forming an interconnect structure over the oxide layer;
etching the interconnect structure over the polysilicon layer to define a cavity therein, wherein a cavity width of the cavity is different from a polysilicon width of the polysilicon layer.

16. The method of claim 15 , wherein depositing the oxide layer comprises depositing the oxide layer in direct contact with a portion of the waveguide material.

17. The method of claim 15 , wherein depositing the polysilicon layer comprises depositing a continuous polysilicon layer covering an entirety of the grating.

18. The method of claim 15 , wherein depositing the polysilicon layer comprises depositing a discontinuous polysilicon layer covering a portion of the grating.

19. The method of claim 15 , etching the interconnect structure comprises defining the cavity having the cavity width, and the polysilicon layer occupies about 20% to about 30% of the cavity width.

20. The method of claim 15 , further comprising extending the cavity through the oxide layer and the polysilicon layer, wherein the cavity exposes a sidewall of the polysilicon layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Chen-Hao
• Lu Hau-Yan
• Hsu Sui-Ying
• Lee Yuehying
• Wu Chien-Ying
• Lee Chien-Chang
• Lai Chia-Ping

Classifications

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• G02B6/4204 Primary

  the coupling comprising intermediate optical elements, e.g. lenses, holograms (encapsulated active devices H01S5/02208) · CPC title

• G02B6/30

  for use between fibre and thin-film device · CPC title

• G02B2006/12176

  Etching · CPC title

• G02B6/29317

  Light guides of the optical fibre type · CPC title