Light detecting device and electronic apparatus including shared reset and amplification transistors

Patent metadata

Field	Value
Publication number	US-12047699-B2
Application number	US-202318093159-A
Country	US
Kind code	B2
Filing date	Jan 4, 2023
Priority date	Jan 28, 2010
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A solid-state imaging device includes a pixel region in which shared pixels which share pixel transistors in a plurality of photoelectric conversion portions are two-dimensionally arranged. The shared pixel transistors are divisionally arranged in a column direction of the shared pixels, the pixel transistors shared between neighboring shared pixels are arranged so as to be horizontally reversed or/and vertically crossed, and connection wirings connected to a floating diffusion portion, a source of a reset transistor and a gate of an amplification transistor in the shared pixels are arranged along the column direction.

First claim

What is claimed is:

1. A light detecting device, comprising:
a first unit including:
first photoelectric conversion regions;
a first floating diffusion;
a first reset transistor shared by the first photoelectric conversion regions; and
a first amplification transistor shared by the first photoelectric conversion regions, and

a second unit disposed adjacent to the first unit, the second unit including:
second photoelectric conversion regions;
a second floating diffusion;
a second reset transistor shared by the second photoelectric conversion regions; and
a second amplification transistor shared by the second photoelectric conversion regions,

wherein
the first amplification transistor and the second reset transistor are arranged along a first line in a plan view,
the first reset transistor and the second amplification transistor are arranged along a second line in the plan view, and
the first line is parallel to the second line in the plan view.

2. The light detecting device according to claim 1 , wherein
the first and second photoelectric conversion regions are respectively arranged along a third line and a fourth line that are perpendicular to the first and second lines in the plan view.

3. The light detecting device according to claim 1 , wherein
the first unit includes a first wiring connected to the first floating diffusion, a gate of the first amplification transistor and a drain of the first reset transistor.

4. The light detecting device according to claim 3 , wherein
the second unit includes a second wiring connected to the second floating diffusion, a gate of the second amplification transistor, and a drain of the second reset transistor.

5. The light detecting device according to claim 4 , wherein
the first wiring mirrors the second wiring about an axis.

6. An electronic apparatus comprising
the light detecting device according to claim 1 .

7. The electronic apparatus according to claim 6 , wherein
the first and second photoelectric conversion regions are respectively arranged along a third line and a fourth line that are perpendicular to the first and second lines in the plan view.

8. The electronic apparatus according to claim 6 , wherein
the first unit includes a first wiring connected to the first floating diffusion, a gate of the first amplification transistor and a drain of the first reset transistor.

9. The electronic apparatus according to claim 8 , wherein
the second unit includes a second wiring connected to the second floating diffusion, a gate of the second amplification transistor, and a drain of the second reset transistor.

10. The electronic apparatus according to claim 9 , wherein
the first wiring mirrors the second wiring about an axis.

Assignees

• Sony Group Corp

Inventors

• Kido Hideo
• Yamamoto Atsuhiko
• Yamada Akihiro

Classifications

• H04N25/767 Primary

  Horizontal readout lines, multiplexers or registers · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/7795

  Circuitry for generating timing or clock signals · CPC title

• H10F39/802 Primary

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title

• H10F39/8037 Primary

  the integrated elements comprising a transistor · CPC title