Semiconductor device protection using an anti-reflective layer

Patent metadata

Field	Value
Publication number	US-12046509-B2
Application number	US-202017128866-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Dec 21, 2020
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a metallic layer may be formed over a semiconductor substrate. An anti-reflective layer may be formed over the metallic layer. A passivation layer may be formed over the anti-reflective layer. An opening may be formed in the passivation layer to expose the anti-reflective layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a metallic layer over a semiconductor substrate;
forming an anti-reflective layer over the metallic layer;
forming a passivation layer over the anti-reflective layer, wherein the passivation layer is in direct contact with the anti-reflective layer, wherein the passivation layer comprises a photopatternable material; and
exposing the anti-reflective layer by forming an opening in the passivation layer in direct contact with the anti-reflective layer.

2. The method of claim 1 , wherein:
the anti-reflective layer is in direct contact with the metallic layer.

3. The method of claim 1 , wherein:
forming the metallic layer comprises forming an unstructured metallic layer.

4. The method of claim 3 , comprising:
after forming the anti-reflective layer and before forming the passivation layer, structuring the anti-reflective layer and the unstructured metallic layer.

5. The method of claim 1 , wherein:
the passivation layer is in direct contact with an anti-reflective portion that is not over the metallic layer.

6. The method of claim 1 , wherein:
the anti-reflective layer comprises an amorphous silicon material.

7. The method of claim 1 , wherein:
the photopatternable material comprises a photopatternable inorganic-organic hybrid material.

8. The method of claim 7 , wherein:
the photopatternable inorganic-organic hybrid material comprises a photopatternable silicon material.

9. The method of claim 7 , wherein:
the photopatternable inorganic-organic hybrid material comprises a photopatternable organic modified ceramic material.

10. The method of claim 1 , wherein:
the passivation layer is in direct contact with the semiconductor substrate.

11. The method of claim 1 , wherein:
the photopatternable material comprises a photopatternable silicone material.

12. A semiconductor device, comprising:
a metallic layer overlying and in direct contact with a semiconductor substrate;
an anti-reflective layer overlying the metallic layer;
a passivation layer overlying and in direct contact with the anti-reflective layer, wherein the passivation layer comprises a photopatternable material; and
a conductive structure extending through the passivation layer in direct contact with the anti-reflective layer.

13. The semiconductor device of claim 12 , wherein:
the metallic layer is a structured metallic layer.

14. The semiconductor device of claim 13 , wherein:
the anti-reflective layer is a structured anti-reflective layer.

15. The semiconductor device of claim 13 , wherein:
the anti-reflective layer is an unstructured anti-reflective layer.

16. The semiconductor device of claim 12 , wherein:
the anti-reflective layer comprises an amorphous silicon material.

17. The semiconductor device of claim 12 , wherein:
the passivation layer comprises the spin-coatable material.

18. The semiconductor device of claim 12 , wherein:
the photopatternable material comprises a photopatternable inorganic-organic hybrid material.

19. The semiconductor device of claim 12 , wherein:
the conductive structure is electrically coupled to the metallic layer.

20. The semiconductor device of claim 12 , wherein:
the photopatternable material comprises a photopatternable silicone material.

21. A semiconductor device, comprising:
a metallic layer overlying and in direct contact with a semiconductor substrate;
an anti-reflective layer overlying the metallic layer; and
a passivation layer overlying and in direct contact with the anti-reflective layer, wherein an opening in the passivation layer exposes at least one of the anti-reflective layer in direct contact with the anti-reflective layer or the metallic layer in direct contact with the semiconductor substrate.

22. A method of manufacturing a semiconductor device, comprising:
forming a metallic layer over a semiconductor substrate;
forming an anti-reflective layer over the metallic layer;
forming a passivation layer over the anti-reflective layer, wherein the passivation layer is in direct contact with the anti-reflective layer and at least one of the semiconductor substrate or an anti-reflective portion that is not over the metallic layer; and
exposing the anti-reflective layer by forming an opening in the passivation layer in direct contact with the anti-reflective layer.

23. The method of claim 22 , wherein:
the passivation layer is in direct contact with the anti-reflective portion that is not over the metallic layer.

24. The method of claim 22 , wherein:
the passivation layer is in direct contact with the semiconductor substrate.

Assignees

• Infineon Technologies Ag

Inventors

• Voss Stephan
• Breymesser Alexander
• Hof Eva-Maria
• Plappert Mathias
• Schaeffer Carsten

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/031 Primary

  of conductive parts of the interconnections · CPC title

• H10W74/131 Primary

  the semiconductor body being only partially enclosed · CPC title

• H01L23/564

  Electricity · mapped topic