Manufacturing method of a semiconductor device

Patent metadata

Field	Value
Publication number	US-12046480-B2
Application number	US-202016940264-A
Country	US
Kind code	B2
Filing date	Jul 27, 2020
Priority date	Aug 28, 2015
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first section of a conductive post over the substrate;
disposing a semiconductor die over the substrate after the forming of the first section of the conductive post;
forming a first portion of a dielectric layer to surround and in contact with a sidewall of the semiconductor die, wherein a top surface of the first portion of the dielectric layer is lower than a top surface of the semiconductor die;
forming a second section of the conductive post coupled to the first section over the top surface of the first portion of the dielectric layer after the disposing of the semiconductor die;
forming a third section of the conductive post coupled to the second section after the disposing of the semiconductor die;
forming a second portion of the dielectric layer over the first portion of the dielectric layer to surround and in contact with the sidewall of the semiconductor die; and
removing the substrate.

2. The method of claim 1 , wherein the first section of the conductive post and the third section of the conductive post are extended along a direction perpendicular to a surface of the substrate.

3. The method of claim 2 , wherein the second section of the conductive post is extended along a direction parallel with the surface of the substrate.

4. The method of claim 1 , wherein the first section of the conductive post and the third section of the conductive post are between the semiconductor die and the second section of the conductive post.

5. The method of claim 1 , wherein the first section, the second section and the third section of the conductive post are separated from the semiconductor die.

6. The method of claim 1 , further comprising:
forming a patterned layer comprising an opening over the substrate; and
filling the opening with a conductive material,
wherein the first section of the conductive post is formed on the conductive material.

7. The method of claim 1 , wherein the first portion of the dielectric layer and the second portion of the dielectric layer comprise a same material.

8. The method of claim 1 , wherein a top surface of the second portion of the dielectric layer is aligned with a top surface of the third section of the conductive post and the top surface of the semiconductor die.

9. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a ground terminal over the substrate;
forming a plurality of conductive posts over the substrate;
disposing a first semiconductor die and a second semiconductor die over the substrate after the forming of the plurality of conductive posts;
surrounding a sidewall of the first semiconductor die and a sidewall of the second semiconductor die with a first molding;
forming a conductive structure over the first semiconductor die, the second semiconductor die and the first molding, wherein the conductive structure has a middle region between the first semiconductor and the second semiconductor die, and the conductive structure comprises a first conductive trace coupled to one of the conductive posts and a second conductive trace in the middle region, and the second conductive trace is separated from the first conductive trace and the plurality of conductive posts;
disposing an electronic component over the first semiconductor die, the second semiconductor die, a portion of the conductive structure, and the first molding;
disposing a second molding over the conductive structure, wherein the second molding surrounds and is in contact with a sidewall of the electronic component;
removing the substrate;
performing a multi-staged cleaving operation on the middle region of the conductive structure to singulate an integrated semiconductor package after the removing of the substrate; and
forming an electric magnetic interference (EMI) shield.

10. The method of claim 9 , wherein the first molding is in contact with the sidewall of the first semiconductor die and the sidewall of the second semiconductor die.

11. The method of claim 9 , wherein the multi-staged cleaving operation comprises:
performing a coarse cut to make a first cleave penetrating the second molding to expose the first molding; and
performing a fine cut to make a second cleave penetrating the first molding,
wherein a width of the first cleave is greater than a width of the second cleave, and the second molding has a tapered sidewall after the multi-staged cleaving operation.

12. The method of claim 11 , wherein the EMI shield covers a top surface and the tapered sidewall of the second molding, a sidewall of the first molding and a sidewall of the conductive trace.

13. The method of claim 9 , wherein the multi-staged cleaving operation comprises:
performing a coarse cut to make a first cleave penetrating the first molding to expose the second molding; and
performing a fine cut to make a second cleave penetrating the second molding,
wherein a width of the first cleave is greater than a width of the second cleave, and the first molding has a tapered sidewall after the multi-staged cleaving operation.

14. The method of claim 13 , wherein the EMI shield covers a top surface and a sidewall of the second molding, the tapered sidewall of the first molding and a sidewall of the conductive trace.

15. The method of claim 9 , wherein the EMI shield is coupled to the ground terminal through the first conductive trace and one of the conductive posts.

16. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a plurality of conductive posts over the substrate;
disposing a first semiconductor die and a second semiconductor die over the substrate after the forming of the conductive posts;
forming a first molding surrounding the first semiconductor die, the second semiconductor die and the conductive posts;
forming a conductive structure having a middle region between the first semiconductor die and the second semiconductive die, wherein the conductive structure comprises a first conductive trace coupled to one of the conductive posts and a second conductive trace in the middle region and separated from the conductive posts, wherein at least one of the first conductive trace and the second conductive trace is in contact with the semiconductor die;
disposing an electronic component over the first semiconductor die, the second semiconductor die, a portion of the first conductive trace, the second conductive trace, and the first molding;
disposing a second molding over the conductive structure, wherein the second molding surrounds and in contact with sidewalls of the electronic component; and
removing the substrate.

17. The method of claim 16 , wherein the first molding is in contact with the first semiconductor die, the second semiconductor die and the conductive posts.

18. The method of claim 16 , further comprising performing a multi-staged cleaving operation to singulate an integrated semiconductor package.

19. The method of claim 16 , further comprising forming an electric magnetic interference (EMI) shield covering a top surface and a sidewall of the second molding and a sidewall of the first molding.

20. The method of claim 19 , wherein the EMI shield is coupled to a ground terminal through the first conductive trace and one of the conductive posts.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Shou Zen
• Lu Chun-Lin
• Wu Kai-Chiang
• Yang Ching-Feng
• Chen Vincent
• Wang Chuei-Tang
• Wang Yen-Ping
• Chen Hsien-Wei
• Lin Wei-Ting

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title