Integrated assemblies and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-12041779-B2
Application number	US-202217678983-A
Country	US
Kind code	B2
Filing date	Feb 23, 2022
Priority date	Apr 30, 2020
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

First claim

We claim:

1. A method of forming an integrated assembly, comprising:
forming a vertical stack of alternating first and second levels; the first levels comprising first material and the second levels comprising second material;
forming an opening to extend through the stack, the opening having a peripheral sidewall;
forming a liner along the peripheral sidewall; the liner being a carbon-containing material; the liner having first regions along the first levels and second regions along the second levels;
forming dielectric-barrier material adjacent the liner;
forming charge-blocking material adjacent the dielectric-barrier material;
forming charge-storage material adjacent the charge-blocking material;
forming tunneling material adjacent the charge-storage material;
forming channel material adjacent the tunneling material;
removing the second material to leave voids between the first levels, and to expose the second regions of the liner;
oxidizing the exposed second regions of the liner to form oxidized segments of the liner; the oxidized segments of the liner being first segments of the liner; the first segments of the liner vertically alternating with second segments of the liner;
removing the first segments of the liner to expose regions of the dielectric-barrier material; and
forming conductive levels within the voids; the conductive levels having front ends with front surfaces along and directly against the exposed regions of the dielectric-barrier material.

2. The method of claim 1 wherein the first segments of the liner have terminal portions which extend beyond the second levels to be along the first levels.

3. The method of claim 2 wherein said terminal portions extend beyond the second levels by at least about 1 nm.

4. The method of claim 1 wherein the carbon-containing material comprises SiOC, where the chemical formula indicates primary constituents rather than a specific stoichiometry; and wherein the carbon is present to a concentration within a range of from about 4 at % to about 20 at %.

5. The method of claim 1 wherein the carbon-containing material comprises SiC, where the chemical formula indicates primary constituents rather than a specific stoichiometry; and wherein the carbon is present to a concentration within a range of from about 4 at % to about 20 at %.

6. The method of claim 1 wherein the carbon-containing material comprises SiCN, where the chemical formula indicates primary constituents rather than a specific stoichiometry; and wherein the carbon is present to a concentration within a range of from about 1 ppm to about 5 at %.

7. The method of claim 1 wherein the first material is silicon dioxide and the second material is silicon nitride.

8. The method of claim 1 wherein the voids are first voids, and further comprising removing the first material to leave second voids.

9. The method of claim 1 wherein the exposed regions of the dielectric-barrier material are first regions of the dielectric-barrier material; wherein the voids are first voids; and further comprising:
removing the first material to leave second voids, the second voids exposing the second segments of the liner;
oxidizing the exposed second segments of the liner;
removing the oxidized second segments of the liner to expose second regions of the dielectric-barrier material;
lining the second voids with sacrificial material to narrow the second voids;
extending the narrowed second voids through the second regions of the dielectric-barrier material, through the charge-blocking material and through the charge-storage material; and
removing the sacrificial material.

10. A method of forming an integrated assembly, comprising:
forming a vertical stack of alternating first and second levels; the first levels comprising first material and the second levels comprising second material;
forming an opening to extend through the stack, the opening having a peripheral sidewall;
forming dielectric-barrier material adjacent the peripheral sidewall;
forming charge-blocking material adjacent the dielectric-barrier material;
forming charge-storage material adjacent the charge-blocking material;
forming tunneling material adjacent the charge-storage material;
forming channel material adjacent the tunneling material;
removing the second material to leave first voids between the first levels;
forming conductive levels within the first voids; the conductive levels having front ends with front surfaces; the front surfaces being along and directly against the dielectric-barrier material;
removing the first material to leave second voids;
lining the second voids with sacrificial material to narrow the second voids;
extending the narrowed second voids through the dielectric-barrier material, the charge-blocking material and the charge-storage material; and
removing the sacrificial material.

11. The method of claim 10 further comprising forming a liner material along the peripheral sidewall, and wherein the dielectric-barrier material is formed along the liner material.

12. The method of claim 11 wherein the liner material comprises metal.

13. The method of claim 12 wherein said metal comprises one or both of tungsten and ruthenium.

14. The method of claim 11 wherein the liner material comprises carbon.

15. The method of claim 14 wherein the liner material comprises the carbon in combination with one or more of silicon, oxygen and nitrogen.

16. The method of claim 15 wherein the liner material comprises SiOC, where the chemical formula indicates primary constituents rather than a specific stoichiometry; and wherein the carbon is present to a concentration within a range of from about 4 at % to about 20 at %.

17. The method of claim 15 wherein the liner material comprises SiC, where the chemical formula indicates primary constituents rather than a specific stoichiometry; and wherein the carbon is present to a concentration within a range of from about 4 at % to about 20 at %.

18. The method of claim 15 wherein the liner material comprises SiCN, where the chemical formula indicates primary constituents rather than a specific stoichiometry; and wherein the carbon is present to a concentration within a range of from about 1 ppm to about 5 at %.

Assignees

• Micron Technology Inc

Inventors

• Surthi Shyam
• Shrotri Kunal
• Thorum Matthew

Classifications

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title