Semiconductor apparatus mounted electrically connected to a plurality of external terminals by a lead

Patent metadata

Field	Value
Publication number	US-12040258-B2
Application number	US-201917439401-A
Country	US
Kind code	B2
Filing date	Mar 25, 2019
Priority date	Mar 25, 2019
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A semiconductor apparatus according to the present invention is a semiconductor apparatus on which a plurality of external terminals are disposed. The semiconductor apparatus includes: a first lead portions having die pads, first outer leads and first inner leads; chips; second lead portions having second outer leads and second inner lead; and a resin. On at least one of the first inner leads, the second inner leads and the die pads, a terminal temperature equalizing structure which restricts a heat transfer amount of heat transferred from the chips to predetermined external terminals, and equalizes respective terminal temperatures of a plurality of external terminals is formed.
According to the semiconductor apparatus of the present invention, it is possible to prevent specific external terminals from becoming extremely high temperature when the semiconductor apparatus is mounted.

First claim

The invention claimed is:

1. A semiconductor apparatus provided with a plurality of external terminals, the semiconductor apparatus comprising:
a first lead portion including: a die pad, a first outer lead forming an outermost one of the plurality of external terminals arranged in a predetermined direction, and a first inner lead connecting the die pad and the first outer lead to each other;
a chip mounted on the die pad connecting to the first outer lead, the chip having a surface electrode on a surface of the chip on a side opposite to a die pad side;
a second lead portion including: a second outer lead forming another external terminal of the plurality of external terminals, and a second inner lead being connected to the surface electrode via a clip lead;
a resin sealing the die pad, the first inner lead, the chip and the second inner lead, a heat radiation fin being mountable on the semiconductor apparatus at a position adjacently to the resin; and
a terminal temperature equalizing structure having a cutout or a hole in the first inner lead between the die pad and the first outer lead forming the outermost one of the plurality of external terminals, the terminal temperature equalizing structure being configured to restrict a heat transfer amount of heat from the chip to the outermost one of the plurality of external terminals and equalize respective terminal temperatures of the plurality of external terminals.

2. The semiconductor apparatus according to claim 1 , wherein the cutout or the hole is at a position where a current path through which a current flows in the first inner lead or the second inner lead is formed into a roundabout path.

3. The semiconductor apparatus according to claim 2 , wherein the cutout or the hole is at a position where the current path through which the current configured to flow in the first inner lead or the second inner lead is in a crank shape.

4. The semiconductor apparatus according to claim 1 , wherein a thickness of the clip lead is smaller than both a thickness of the first lead portion and a thickness of the second lead portion.

5. The semiconductor apparatus according to claim 1 , wherein assuming a heat resistance between one of the plurality of external terminals and one chip which forms the chip connected to the external terminal as a chip external-terminal heat resistance θ when one of the plurality of external terminals is connected to the one chip, and
assuming a sum of heat resistances between one of the plurality of external terminals and two or more chips which form the chip connected to the one of the plurality of external terminals as the chip external-terminal heat resistance θ when one of the plurality of external terminals is connected to the two or more chips,
the chip external-terminal heat resistances θ are equal among the respective external terminals.

6. The semiconductor apparatus according to claim 1 , wherein as viewed in a cross section, the die pad includes a depressed portion for positioning the die pad closer to the heat radiation fin than the first inner lead on a side where the heat radiation fin is located.

7. The semiconductor apparatus according to claim 1 , wherein the semiconductor apparatus is a bridge diode.

8. The semiconductor apparatus according to claim 1 , wherein the plurality of external terminals are four external terminals arranged parallel to each other,
four chips are provided as the chip,
two first lead portions each having two die pads are provided as the first lead portion,
the two first lead portions each have a portion formed in a U shape by the first inner lead and the two die pads, and the portions which are formed in a U shape are combined with each other in a staggered manner, and the respective die pads are disposed in a row along a predetermined direction, and
the cutout or the hole is formed in both the first inner leads of the two first lead portions.

9. The semiconductor apparatus according to claim 1 , wherein the plurality of external terminals are three external terminals arranged parallel to each other,
two chips are provided as the chip,
two first lead portions each having one die pad are provided as the first lead portion,
one second lead portion is provided as the second lead portion, and
the cutout or the hole is formed in all of the first inner leads of the two first lead portions and the second inner lead of the second lead portion.

10. A lead frame comprising the first lead portion and the second lead portion used in the semiconductor apparatus according to claim 1 .

11. A power source apparatus comprising the semiconductor apparatus according to claim 1 .

12. The semiconductor apparatus according to claim 1 , wherein
the first lead portion further includes:
another die pad,
another first outer lead forming another outermost one of the plurality of external terminals in the predetermined line, and
another first inner lead connecting another die pad and another first outer lead to each other;

another chip mounted on another die pad connecting to another first outer lead, another chip having a surface electrode on a surface of the chip on a side opposite to a die pad side; wherein
another terminal temperature equalizing structure having another cutout or another hole in another first inner lead between another die pad and another first outer lead forming the outermost one of the plurality of external terminals, the terminal temperature equalizing structure being configured to restrict a heat transfer amount of heat from another chip to another outermost one of the plurality of external terminals and equalize respective terminal temperatures of the plurality of external terminals.

13. The semiconductor apparatus according to claim 1 , wherein the first outer lead and the die pad are in a direction perpendicular to the predetermined direction in which the plurality of the external terminals is arranged.

14. A semiconductor apparatus provided with a plurality of external terminals, the semiconductor apparatus comprising:
a first lead portion including: a die pad, a first outer lead forming one of the plurality of external terminals, and a first inner lead connecting the die pad and the first outer lead to each other;
a chip mounted on the die pad, a surface electrode being formed on a surface of the chip on a side opposite to a die pad side;
a second lead portion including: a second outer lead forming another external terminal of the plurality of external terminals, and a second inner lead being connected to the surface electrode via a clip lead; and
a resin sealing the die pad, the first inner lead, the chip and the second inner lead, a heat radiation fin being mountable on the semiconductor apparatus at a position disposed adjacently to the resin, wherein
a terminal temperature equalizing structure which restricts a heat transfer amount of heat from the chip to a predetermined external terminal of the plurality of external terminals and equalizes respective terminal temperatures of the plurality of external terminals is formed on at least one of the first inner lead and the second inner lead, wherein
the terminal temperature equalizing structure has a cutout or a hole formed in at least one of the first inner lead and the second inner lead, and
the plurality of external terminals are five external terminals, six chips are provided as the chip,
three first lead portions each having two die pads are provided as the first lead portion,
two second lead portions are provided as the second lead portion,
the respective second inner leads are connected to any one of two chips mounted on the respective

Assignees

• Shindengen Electric Mfg

Inventors

• Uchida Naoto
• Kobayashi Yoshimasa
• Arai Toshikazu

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W72/076

  of strap connectors · CPC title

• H10W72/60

  Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title