Semiconductor memory device for applying voltage to select line based on number of times program loops are performed and method of operating the same

Patent metadata

Field	Value
Publication number	US-12040022-B2
Application number	US-202117535220-A
Country	US
Kind code	B2
Filing date	Nov 24, 2021
Priority date	Jun 25, 2021
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A method of operating a semiconductor memory device includes performing a plurality of program loops for programming selected memory cells among a plurality of memory cells. Each of the plurality of program loops includes a program phase and a verify phase. The program phase includes setting a state of a select line connected to a selected memory block including the selected memory cells, wherein setting the state of the select line connected to the selected memory block comprises applying a voltage to the select line based on a program progress state of the selected memory cells, setting a state of a bit line connected to the selected memory block, applying a program voltage to a selected word line among word lines connected to the selected memory block and applying a pass voltage to an unselected word line.

First claim

What is claimed is:

1. A method of operating a semiconductor memory device for programming selected memory cells among a plurality of memory cells, the method comprising performing a plurality of program loops with each of the plurality of program loops including a program phase and a verify phase, wherein the program phase comprises:
applying a first voltage or a second voltage to a select line coupled to a selected memory block including the selected memory cells based on a number of times the plurality of program loops is performed;
setting a state of a bit line coupled to the selected memory block;
applying a program voltage to a selected word line among word lines coupled to the selected memory block while the first voltage or the second voltage is applied to the select line; and
applying a pass voltage to an unselected word line among the word lines coupled to the selected memory block.

2. The method of claim 1 , wherein applying the first voltage or the second voltage to the select line comprises:
checking program states of which a program is completed in the verify phase of an immediately previous program loop; and
applying the first voltage to the select line, when a program of memory cells to be programmed to an i-th program state is not completed among first to (2 N −1)-th program states,
wherein each of the plurality of memory cells is capable of storing N bits of data, N is a natural number greater than 1, and i is a natural number greater than 0 and less than (2 N −1).

3. The method of claim 2 , wherein applying the first voltage or the second voltage to the select line comprises applying the second voltage different from the first voltage to the select line, when the program of the memory cells to be programmed to the i-th program state is completed.

4. The method of claim 3 , wherein the select line is a drain select line.

5. The method of claim 3 , wherein the select line is a source select line.

6. The method of claim 3 , wherein the second voltage is less than the first voltage.

7. The method of claim 3 , wherein the second voltage is greater than the first voltage.

8. The method of claim 2 , wherein N is 2 and i is 2.

9. The method of claim 2 , wherein N is 3 and i is 6.

10. The method of claim 1 , wherein the verify phase comprises:
applying a pre-verify voltage to a word line coupled to the selected memory cells; and
applying a main verify voltage greater than the pre-verify voltage to the word line coupled to the selected memory cells.

11. The method of claim 10 , wherein the verify phase further comprises determining memory cells having a threshold voltage higher than the main verify voltage as program inhibit cells.

12. The method of claim 11 , wherein the verify phase further comprises:
determining memory cells having a threshold voltage lower than the pre-verify voltage as first program allowable cells; and
determining memory cells having a threshold voltage higher than the pre-verify voltage and lower than the main verify voltage as second program allowable cells.

13. The method of claim 12 , wherein setting the state of the bit line coupled to the selected memory block comprises:
applying a first program allowable voltage to a bit line coupled to the first program allowable cells; and
applying a second program allowable voltage greater than the first program allowable voltage to a bit line coupled to the second program allowable cells.

14. The method of claim 13 , wherein setting the state of the bit line coupled to the selected memory block including the selected memory cells further comprises applying a program inhibit voltage greater than the second program allowable voltage to a bit line coupled to the program inhibit cells.

15. A semiconductor memory device comprising:
a memory block including a plurality of memory cells each capable of storing N bits of data, wherein N is a natural number greater than 1;
a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells included in the memory block; and
a control logic circuit configured to control the program operation performed on the selected memory cells,
wherein the program operation includes a plurality of program loops each including a program phase and a verify phase, and
wherein, in the program phase, the control logic circuit is configured to control the peripheral circuit to:
apply a first voltage or a second voltage to a select line coupled to the memory block based on a number of times the plurality of program loops is performed;
set a state of a bit line coupled to a selected memory block;
apply a program voltage to a selected word line among word lines coupled to the selected memory block while the first voltage or the second voltage is applied to the select line; and
apply a pass voltage to an unselected word line.

16. The semiconductor memory device of claim 15 , wherein the control logic circuit is configured to control the peripheral circuit to apply the first voltage or the second voltage to the select line by checking program states of which a program is completed in the verify phase of an immediately previous program loop, and controlling the peripheral circuit to apply the first voltage to the select line, when a program of memory cells to be programmed to an i-th program state is not completed among first to (2 N −1)-th program states, and wherein i is a natural number greater than 0 and less than (2 N −1).

17. The semiconductor memory device of claim 16 , wherein the control logic circuit is configured to control the peripheral circuit to apply the second voltage different from the first voltage to the select line, when the program of the memory cells to be programmed to the i-th program state is completed.

18. The semiconductor memory device of claim 17 , wherein:
the select line is a drain select line; and
the second voltage is less than the first voltage.

19. The semiconductor memory device of claim 15 , wherein the control logic circuit is configured to, in the verify phase:
control the peripheral circuit to apply a pre-verify voltage to a word line coupled to the selected memory cells and apply a main verify voltage greater than the pre-verify voltage to the word line coupled to the selected memory cells;
determine memory cells having a threshold voltage higher than the main verify voltage as program inhibit cells;
determine memory cells having a threshold voltage lower than the pre-verify voltage as first program allowable cells; and
determine memory cells having a threshold voltage higher than the pre-verify voltage and lower than the main verify voltage as second program allowable cells.

20. The semiconductor memory device of claim 19 , wherein the control logic circuit is configured to, in a process of setting the state of the bit line coupled to the selected memory block, control the peripheral circuit to:
apply a first program allowable voltage to a bit line coupled to the first program allowable cells;
apply a second program allowable voltage greater than the first program allowable voltage to a bit line coupled to the second program allowable cells; and
apply a program inhibit voltage greater than the second program allowable voltage to a bit line coupled to the program inhibit cells.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/24

  Bit-line control circuits · CPC title