Method of testing a suspend operation

Patent metadata

Field	Value
Publication number	US-12039186-B2
Application number	US-202217875569-A
Country	US
Kind code	B2
Filing date	Jul 28, 2022
Priority date	Nov 11, 2021
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A method of testing a suspend operation, the method including: determining whether to transfer a suspend sampling signal to a suspend command circuit at a time point prior to each of a plurality of suspend operation time points stored in a sequence operation circuit; transferring the suspend sampling signal from the sequence operation circuit to the suspend command circuit; generating an internal suspend operation command based on the suspend sampling signal; transferring the internal suspend operation command from the suspend command circuit to the sequence operation circuit; performing suspend operations for all the plurality of suspend operation time points in response to the internal suspend operation command; and determining whether the suspend operations are performed at all of the suspend operation time points.

First claim

What is claimed is:

1. A method of testing a suspend operation, the method comprising:
determining whether to transfer a suspend sampling signal to a suspend command circuit at a time point prior to each of a plurality of suspend operation time points stored in a sequence operation circuit;
transferring the suspend sampling signal from the sequence operation circuit to the suspend command circuit;
generating an internal suspend operation command based on the suspend sampling signal;
transferring the internal suspend operation command from the suspend command circuit to the sequence operation circuit;
performing suspend operations for all the plurality of suspend operation time points in response to the internal suspend operation command; and
determining whether the suspend operations are performed at all of the suspend operation time points.

2. The method of claim 1 , wherein the sequence operation circuit outputs a command for performing a programming operation or a read operation on a memory cell corresponding to a predetermined address, using a program/read control circuit, while performing the suspend operation.

3. The method of claim 2 , wherein the sequence operation circuit outputs a resume command using a resume control circuit after performing the programming operation or the read operation.

4. The method of claim 1 , wherein a time interval between the suspend operations performed at all of the suspend operation time points is not constant.

5. The method of claim 1 , wherein a programming operation includes a plurality of loops, and all of the suspend operation time points in each of the plurality of loops during an execution of the programming operation includes a first program suspend operation time point, a second program suspend operation time point, and a plurality of third program suspend operation time points, and
the first program suspend operation time point is after a bit line setup is performed, the second program suspend operation time point is after a program voltage is applied, and each of the plurality of third program suspend operation time points is after at least one of a plurality of program verification operations is performed.

6. The method of claim 5 , wherein a resume operation time point corresponding to the second program suspend operation time point and resume operation time points corresponding to the plurality of third program suspend operation time points, respectively, in any one of the plurality of loops, and a resume operation time point corresponding to the first program suspend operation in a subsequent loop are identical to each other.

7. The method of claim 5 , wherein the sequence operation circuit includes a suspend control circuit for controlling the suspend operation to be performed once at each of the first program suspend operation time point and the plurality of third program suspend operation time points.

8. The method of claim 1 , wherein an erase operation includes a plurality of loops, and all of the suspend operation time points in each of the plurality of loops during the erase operation include a first erase suspend operation time point, a second erase suspend operation time point, a plurality of third erase suspend operation time points, a fourth erase suspend operation time point, and a plurality of fifth erase suspend operation time points, and
the first erase suspend operation time point is after a pre-programming operation, the second erase suspend operation time point is after a ramping operation, each of the plurality of third erase suspend operation time points is a time point when an erase voltage is applied, the fourth erase suspend operation time point is after an erase verification operation is performed, and the plurality of fifth erase suspend operation time points are after a defense code is executed.

9. The method of claim 8 , wherein in any one of the plurality of loops, a resume operation time point corresponding to the second erase suspend operation time point and resume operation time points corresponding to the plurality of third erase suspend operations, respectively, are identical to each other.

10. The method of claim 8 , wherein in any one of the plurality of loops, resume operation time points corresponding to the plurality of fifth erase suspend operations, respectively, are identical to each other.

11. The method of claim 8 , wherein the sequence operation circuit includes a suspend control circuit for controlling the suspend operation to be performed once at each of the first erase suspend operation time point, the second erase suspend operation time point, the plurality of third erase suspend operation time points, and the plurality of fifth erase suspend operation time points.

12. A method of testing a suspend operation, comprising:
designating a memory cell to perform a programming operation and an erase operation, and determining whether to automatically perform a resume operation after a read operation and the suspend operation on the memory cell;
applying a programming command or an erase command;
transferring a suspend sampling signal to a suspend command circuit to perform the suspend operation once at each of all suspend operation time points by using a suspend control circuit included in a sequence operation circuit;
determining whether the suspend operation is completed at all of the suspend operation time points, using an internal suspend command generated based on the suspend sampling signal; and
reading data stored in the memory cell.

13. The method of claim 12 , further comprising reading the data stored in the memory cell and determining whether an operation according to the programming command or the erase command is performed, when the suspend operation is completed at all of the suspend operation time points.

14. The method of claim 12 , further comprising reading the data stored in the memory cell and determining whether the data stored in the memory cell is read when the suspend operation is not completed at all of the suspend operation time points.

15. The method of claim 14 , further comprising determining again whether the suspend operation is completed at suspend operation time points after a resume operation is resumed, when the data stored in the memory cell is read.

16. A method of testing a suspend operation, comprising:
setting a number of test cycles to perform a suspend test on a memory device including a memory cell area and a peripheral circuit area;
performing a programming operation or an erase operation on the memory cell area;
comparing the set number of test cycles with a number of the programming operation or the erase operation;
performing the suspend test for all suspend operation time points included in a subsequent operation when the number of the programming operation or the erase operation is greater than the number of test cycles; and
determining whether to perform the suspend operation in the peripheral circuit area based on a result of the suspend test.

17. The method of claim 16 , wherein a sequence operation circuit and a suspend command circuit used to perform the suspend test are activated when the number of the programming operation or the erase operation is greater than the number of the test cycles.

18. The method of claim 16 , wherein, when the number of the programming operation or the erase operation is greater than the number of the test cycles, a first command different from a second command for instructing the programming operation or the erase operation on the memory cell area is applied to perfor

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Suyong
• Park Junyong
• Yun Sangbum
• Park Ilhan

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title