Method for measuring current-voltage characteristic

Patent metadata

Field	Value
Publication number	US-12038468-B2
Application number	US-202017139228-A
Country	US
Kind code	B2
Filing date	Dec 31, 2020
Priority date	Mar 29, 2016
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.

First claim

What is claimed is:

1. A method for measuring a current-voltage characteristic representing a relationship between a drain current and a drain-source voltage of a transistor, the method comprising:
a first data acquisition operation for setting a drain current set value as Id 1 in a sub-operation of setting the drain current set value and for measuring a first gate-source voltage in a sub-operation of measuring a gate-source voltage,
a second data acquisition operation for setting a drain current set value as Id 2 in a sub-operation of setting the drain current set value and for measuring a second gate-source voltage in a sub-operation of measuring a gate-source voltage,
wherein each of the first and second data acquisition operations includes:
a sub-operation of setting a drain current set value and a drain-source voltage set value Vds 1 ;
a sub-operation of arranging a switching transient state wherein the drain-source voltage varies from the set value Vds 1 to substantially close to 0 in turn-ON or from 0 to substantially close to the set value Vds 1 in turn-OFF; and
a sub-operation of measuring a gate-source voltage and a gate current of the transistor in a switching transient state, wherein the gate-source voltage and the gate current remain substantially constant in the switching transient state;
wherein the current-voltage characteristic of the transistor is acquired based on calculation results of a voltage applied to a gate oxide film of the transistor in the switching transient state,

wherein the voltage applied to the gate oxide film of the transistor is calculated using a multiplication of an inner gate resistance value of the transistor multiplied by the gate current in the switching transient state, and
wherein a drain current at another gate-source voltage for the current-voltage characteristics is calculated using a relationship between the drain current Id 1 and a voltage applied to the gate oxide film at the first gate-source voltage and another relationship between the drain current Id 2 and a voltage applied to the gate oxide film at the second gate-source voltage.

2. The method of claim 1 , wherein the drain current and the drain-source voltage are set by use of a voltage source and a current source connected in series with the transistor and a rectifying device connected in parallel with, and in a reverse direction with respect to, the current source.

3. The method of claim 2 , wherein as the current source, an inductive load is used.

4. The method of claim 1 , wherein the transistor is a semiconductor device of which a gradient of the current-voltage characteristic does not become zero even in a saturation region thereof.

5. The method of claim 1 , wherein the drain current remains substantially constant in the switching transient state, and a parasitic inductance (L) contribution to the gate-source voltage by the drain current L(dI d /dt) is substantially 0 in the switching transient state.

6. The method of claim 1
wherein the voltage applied to the gate oxide film of the transistor Vgs(real) is calculated as Vgs(real)=((Vgs,off×Ig,on)−(Vgs,on×Ig,off))/(Ig,on−Ig,off), wherein Vgs,on is the gate-source voltage in turn-ON, Vgs,off is the gate-source voltage in turn-OFF, Ig,on is the gate current in turn-ON, and Ig,off is the gate current in turn-OFF.

7. The method of claim 6 , wherein the drain current and the drain-source voltage are set by use of a voltage source and a current source connected in series with the transistor and a rectifying device connected in parallel with, and in a reverse direction with respect to, the current source.

8. The method of claim 7 , wherein as the current source, an inductive load is used.

9. The method of claim 6 , wherein the current-voltage characteristic of the transistor at the drain-source voltage is acquired using a relation between a drain current and a gate-source voltage, and a drain current at the drain-source voltage is estimated at a point where a gate-source voltage in the relation is equal to the voltage applied to the gate oxide film.

10. The method of claim 6 , wherein the transistor is a semiconductor device of which a gradient of the current-voltage characteristic does not become zero even in a saturation region thereof.

11. The method of claim 6 , wherein the drain current remains substantially constant in the switching transient state, and a parasitic inductance (L) contribution to the gate-source voltage by the drain current L(dI d /dt) is substantially 0 in the switching transient state.

12. The method according to claim 1 , wherein the transistor is an IGBT, the drain is a collector of the IGBT, and the source is an emitter of the IGBT.

13. The method according to claim 6 , wherein the transistor is an IGBT, the drain is a collector of the IGBT, and the source is an emitter of the IGBT.

14. The method according to claim 1 , wherein the transistor is a GaN power transistor.

15. The method according to claim 6 , wherein the transistor is a GaN power transistor.

16. The method according to claim 1 , wherein the transistor is a SiC power transistor.

17. The method according to claim 6 , wherein the transistor is a SiC power transistor.

18. A method for creating a device model of a transistor by parameterizing a current-voltage characteristic of the transistor measured by the method according to claim 12 .

19. A method for creating a device model of a transistor by parameterizing a current-voltage characteristic of the transistor measured by the method according to claim 18 .

20. A method for computer simulation of a circuit including a transistor, wherein a device model of the transistor is created by the method for creating a device model according to claim 18 .

21. A method for computer simulation of a circuit including a transistor, wherein a device model of the transistor is created by the method for creating a device model according to claim 19 .

Assignees

• Rohm Co Ltd

Inventors

• Yanagi Tatsuya
• Otake Hirotaka
• Sakairi Hiroyuki
• Kuroda Naotaka

Classifications

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G01R31/2603

  for curve tracing of semiconductor characteristics, e.g. on oscilloscope · CPC title

• G01R31/2601 Primary

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title