Method of fabricating a superconducting parallel plate capacitor

Patent metadata

Field	Value
Publication number	US-12034404-B2
Application number	US-202117158484-A
Country	US
Kind code	B2
Filing date	Jan 26, 2021
Priority date	May 14, 2015
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.

First claim

The invention claimed is:

1. A method of fabricating a superconducting parallel plate capacitor, the method comprising:
depositing a first superconductive layer, the first superconductive layer comprising a material that is superconductive in a range of critical temperatures;
depositing a first dielectric layer to overlie at least part of the first superconductive layer;
depositing a second superconductive layer to overlie at least part of the dielectric layer, the second superconductive layer comprising a material that is superconductive in the range of critical temperatures;
removing a portion of the second superconductive layer to form at least one structure from the second superconductive layer and to expose at least part of the first dielectric layer;
depositing a second dielectric layer to overlie at least part of the second superconductive layer and at least part of the first dielectric layer;
planarizing the second dielectric layer;
removing at least part of the second dielectric layer to form a first via exposing at least part of the second superconductive layer;
removing at least part of the second dielectric layer and at least part of the first dielectric layer to form a second via exposing at least part of the first superconductive layer;
depositing a first region of a third superconductive layer; and
depositing a second region of the third superconductive layer, wherein the first region of the third superconductive layer is electrically isolated from the second region of the third superconductive layer, the first region of the third superconductive layer is superconductingly connected to at least part of the second superconductive layer by way of the first via, and the second region of the third superconductive layer is superconductingly connected to at least part of the first superconductive layer by way of the second via.

2. The method of claim 1 wherein the first dielectric layer comprises silicon nitride.

3. The method of claim 2 wherein the second dielectric layer comprises silicon dioxide.

4. The method of claim 1 wherein the second dielectric layer comprises silicon dioxide.

5. The method of claim 1 wherein the third superconductive layer comprises niobium.

6. The method of claim 1 wherein the thickness of the first and the second superconductive layers is in the range of about 100 nm to 400 nm, the thickness of the first dielectric layer is in the range of about 10 nm to 100 nm, and the thickness of the second dielectric layer is in the range of about 100 nm to 300 nm.

7. The method of claim 1 wherein the first and the second superconductive layers comprise niobium.

8. The method of claim 7 wherein the first dielectric layer comprises silicon nitride.

9. The method of claim 7 wherein the second dielectric layer comprises silicon dioxide.

10. The method of claim 7 wherein the third superconductive layer comprises niobium.

11. The method of claim 7 wherein the thickness of the first and the second superconductive layers is in the range of about 100 nm to 400 nm, the thickness of the first dielectric layer is in the range of about 10 nm to 100 nm, and the thickness of the second dielectric layer is in the range of about 100 nm to 300 nm.

Assignees

• D Wave Systems Inc
• 1372934 B C Ltd

Inventors

• Berkley Andrew J
• Swenson Loren J
• Volkmann Mark H
• Whittaker Jed D
• Bunyk Paul I
• Spear Peter D
• Rich Christopher B

Classifications

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• H03H7/01

  Frequency selective two-port networks · CPC title

• H01P7/105

  Multimode resonators · CPC title

• H01P7/08

  Strip line resonators · CPC title