Chemical mechanical polishing for copper dishing control

Patent metadata

Field	Value
Publication number	US-12033964-B2
Application number	US-202117411599-A
Country	US
Kind code	B2
Filing date	Aug 25, 2021
Priority date	Aug 25, 2021
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.

First claim

The invention claimed is:

1. A semiconductor processing method comprising:
providing a substrate to a polishing assembly, wherein the substrate comprises:
silicon oxide defining one or more features,
a liner extending across the substrate and within the one or more features, and
a copper-containing layer deposited on the liner and extending within the one or more features;

contacting the substrate with a first slurry and a first platen, wherein the first slurry and the first platen remove a first portion of the copper-containing layer such that a remaining portion of the copper-containing layer is recessed below the liner, which fully separates regions of copper within the one or more features across the substrate;
after contacting the substrate with the first slurry and the first platen, contacting the substrate with a second slurry and a second platen, wherein the second slurry and the second platen remove at least a portion of the liner;
after contacting the substrate with the second slurry and the second platen, contacting the substrate with a third slurry and a third platen, wherein the third slurry and the third platen remove a second portion the copper-containing layer; and
after contacting the substrate with the third slurry and the third platen, contacting the substrate with a fourth slurry and a fourth platen, wherein the fourth slurry and the fourth platen remove at least a portion of silicon oxide, and wherein the fourth slurry is a dilution of the second slurry.

2. The semiconductor processing method of claim 1 , wherein:
the first slurry is the same as the third slurry;
the first platen is the same as the third platen; and
the second platen is the same as the fourth platen.

3. The semiconductor processing method of claim 1 , wherein the fourth slurry is characterized by a slurry concentration of less than or about 50% of the second slurry.

4. The semiconductor processing method of claim 1 , wherein contacting the substrate with the fourth slurry and the fourth platen continues for a period of time of greater than or about 30 seconds.

5. A semiconductor processing method comprising:
contacting a substrate with a first slurry and a first platen, wherein the substrate comprises:
silicon oxide defining one or more features,
a liner extending across the silicon oxide and within the one or more features, and
a copper-containing layer deposited on the liner and extending within the one or more features, wherein the first slurry and the first platen remove a first portion of the copper-containing layer such that a remaining portion of the copper-containing layer is recessed below the liner, which fully separates regions of copper within the one or more features across the substrate;

after contacting the substrate with the first slurry and the first platen, contacting the substrate with a second slurry and a second platen, wherein the second slurry and the second platen remove at least a portion of the liner;
after contacting the substrate with the second slurry and the second platen, contacting the substrate with a third slurry and a third platen, wherein the third slurry and the third platen remove a second portion of the copper-containing layer; and
after contacting the substrate with the third slurry and the third platen, contacting the substrate with a fourth slurry and a fourth platen, wherein the fourth slurry and the fourth platen remove at least a portion of the silicon oxide.

6. The semiconductor processing method of claim 5 , wherein:
the first slurry is the same as the third slurry; and
the first platen is the same as the third platen.

7. The semiconductor processing method of claim 5 , wherein:
the second slurry is the same as the fourth slurry; and
the second platen is the same as the fourth platen.

8. The semiconductor processing method of claim 5 , wherein contacting the substrate with the fourth slurry and the fourth platen further removes a third portion of the copper-containing layer.

9. The semiconductor processing method of claim 5 , wherein the copper-containing layer is characterized by a concave profile within the one or more features in the silicon oxide, and wherein a nadir of the concave profile is within 10 nm of a surface of the silicon oxide in which the one or more features are defined.

10. The semiconductor processing method of claim 5 , wherein contacting the substrate with the fourth slurry and the fourth platen continues for a period of time of greater than or about 10 seconds.

11. The semiconductor processing method of claim 5 , wherein the fourth slurry is characterized by a removal selectivity between silicon oxide and copper of less than or about 2:1.

12. The semiconductor processing method of claim 5 , further comprising:
diluting the second slurry to form the fourth slurry.

13. The semiconductor processing method of claim 12 , wherein the fourth slurry is characterized by a slurry concentration of less than or about 50% of the second slurry.

14. A semiconductor processing method comprising:
providing a substrate to a polishing assembly, wherein the substrate comprises:
silicon oxide defining one or more features recessed from a surface of the silicon oxide,
a liner extending across the silicon oxide and within the one or more features, and
a copper-containing layer deposited on the liner and extending within the one or more features;

polishing the substrate with a first slurry, wherein polishing with the first slurry removes copper to expose the liner across the silicon oxide;
polishing the substrate with a second slurry, wherein polishing with the second slurry removes the liner from the surface of the silicon oxide;
polishing the substrate with a third slurry, wherein polishing with the third slurry recesses the copper a distance within the features, and wherein the copper is characterized by a dish profile having a dish depth; and
polishing the substrate with a fourth slurry, wherein polishing with the fourth slurry removes at least a portion of the silicon oxide and reduces the dish depth of the copper.

15. The semiconductor processing method of claim 14 , wherein:
the first slurry is the same as the third slurry; and
the second slurry is the same as the fourth slurry.

16. The semiconductor processing method of claim 14 , wherein the fourth slurry is characterized by a removal selectivity between silicon oxide and copper of less than or about 1.5:1.

17. The semiconductor processing method of claim 14 , wherein the dish depth after polishing with the third slurry is greater than or about 5 nm, and wherein the dish depth after polishing with the fourth slurry is less than or about 5 nm.

18. The semiconductor processing method of claim 14 , wherein the fourth slurry comprises the second slurry diluted to a concentration of less than or about 40%.

19. The semiconductor processing method of claim 18 , wherein polishing the substrate with the fourth slurry etches silicon oxide at an etch rate of less than or about 15 nm per minute.

20. The semiconductor processing method of claim 19 , wherein polishing the substrate with the fourth slurry is performed for a period of time of greater than or about 30 seconds.

Assignees

• Applied Materials Inc

Inventors

• Sherwood Tyler
• Salfelder Joseph F
• Ahn Ki Cheol
• Ma Kai
• SREENIVASAN Raghav
• Appell Jason

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/054

  by selectively removing parts thereof (H10W20/034 takes precedence) · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10P52/403 Primary

  of conductive or resistive materials · CPC title