Semiconductor device

Patent metadata

Field	Value
Publication number	US-12033718-B2
Application number	US-202217944725-A
Country	US
Kind code	B2
Filing date	Sep 14, 2022
Priority date	Mar 16, 2022
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

A semiconductor device according to an embodiment includes first to fifth interconnects, first to third memory cells, and a control circuit. The control circuit is configured to execute machine learning. Each of the first memory cells, the second memory cells, and the third memory cells includes a resistance changing element. In the machine learning, the control circuit is configured to: execute a write operation using a common write voltage to each of the second memory cells; and after the write operation, input input data to each of the first interconnects, and change a resistance value of at least one third memory cell of the third memory cells based on the input data and a signal output from each of the fifth interconnects based on the input data.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a plurality of first interconnects;
a plurality of second interconnects each intersecting the first interconnects;
a plurality of first memory cells respectively provided at intersections between the first interconnects and the second interconnects, each of the first memory cells being coupled between one of the first interconnects and one of the second interconnects;
a plurality of third interconnects each intersecting the second interconnects, the third interconnects being respectively coupled to the second interconnects via a delay circuit;
a plurality of second memory cells respectively provided at intersections between the third interconnects and the second interconnects, each of the second memory cells being coupled between one of the third interconnects and one of the second interconnects;
a plurality of fourth interconnects respectively coupled to the second interconnects;
a plurality of fifth interconnects each intersecting the fourth interconnects;
a plurality of third memory cells respectively provided at intersections between the fourth interconnects and the fifth interconnects, each of the third memory cells being coupled between one of the fourth interconnects and one of the fifth interconnects; and
a control circuit configured to execute machine learning, wherein
each of the first memory cells, the second memory cells, and the third memory cells includes a resistance changing element, and
in the machine learning, the control circuit is configured to:
execute a write operation using a common write voltage to each of the second memory cells; and
after the write operation, input input data to each of the first interconnects, and change a resistance value of at least one third memory cell of the third memory cells based on the input data and a signal output from each of the fifth interconnects based on the input data.

2. The semiconductor device of claim 1 , wherein
in the write operation, the control circuit is configured to determine a number of pulses of the write voltage to be applied to the second memory cells according to a number of the second interconnects or the third interconnects that are allocated.

3. The semiconductor device of claim 1 , wherein
in the write operation, the control circuit is configured to determine an application time of the write voltage to the second memory cells according to a number of the second interconnects or the third interconnects that are allocated.

4. The semiconductor device of claim 1 , wherein
the control circuit is configured to change a number of the second interconnects according to a type of the input data.

5. The semiconductor device of claim 1 , wherein
the control circuit is configured not to change a resistance value of each of the first memory cells and the second memory cells after the write operation in the machine learning.

6. The semiconductor device of claim 1 , wherein
the first memory cells are used for an input layer of reservoir computing,
the second memory cells are used for a reservoir layer of the reservoir computing, and
the third memory cells are used for an output layer of the reservoir computing.

7. The semiconductor device of claim 1 , wherein
the resist changing element included in each of the first memory cancer cells, the second memory cells, and the third memory cells includes a ferroelectric film.

8. The semiconductor device of claim 7 , wherein
each of the first memory cells, the second memory cells, and the third memory cells contains an oxide of at least one element of a group consisting of titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), aluminum (Al), and zinc (Zn).

9. A semiconductor device comprising:
a plurality of first interconnects;
a plurality of second interconnects each intersecting the first interconnects;
a plurality of first memory cells respectively provided at intersections between the first interconnects and the second interconnects, each of the first memory cells being coupled between one of the first interconnects and one of the second interconnects;
an output circuit including a plurality of output units, the output units including input nodes respectively coupled to the second interconnects;
a plurality of third interconnects each intersecting the second interconnects, the third interconnects being respectively coupled to output nodes of the output units via a delay circuit;
a plurality of second memory cells respectively provided at intersections between the third interconnects and the second interconnects, each of the second memory cells being coupled between one of the third interconnects and one of the second interconnects;
a plurality of fourth interconnects respectively coupled to the output nodes of the output units;
a plurality of fifth interconnects each intersecting the fourth interconnects;
a plurality of third memory cells respectively provided at intersections between the fourth interconnects and the fifth interconnects, each of the third memory cells being coupled between one of the fourth interconnects and one of the fifth interconnects; and
a control circuit configured to execute machine learning, wherein
each of the first memory cells, the second memory cells, and the third memory cells includes a resistance changing element, and
in the machine learning, the control circuit is configured to:
adjust a variation in output of the output units according to a number of the second interconnects; and
after adjusting the variation in output of the output units, input input data to each of the first interconnects, and change a resistance value of at least one third memory cell of the third memory cells based on the input data and a signal output from each of the fifth interconnects based on the input data.

10. The semiconductor device of claim 9 , wherein
each of the output units includes a current-voltage conversion circuit and a differential amplifier circuit, and
the control circuit is configured to adjust the variation in output of the output units by adjusting a variable resistor included in the current-voltage conversion circuit and a reference voltage input to the differential amplifier circuit.

11. The semiconductor device of claim 10 , wherein
the current-voltage conversion circuit includes a first operational amplifier and the variable resistor,
the differential amplifier circuit includes a second operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor, wherein a resistance value of the third resistor corresponds to a resistance value of the first resistor, and a resistance value of the fourth resistor corresponds to a resistance value of the second resistor,
an inverting input of the first operational amplifier is coupled to a corresponding one of the second interconnects, the variable resistor is coupled between an output of the first operational amplifier and the inverting input of the first operational amplifier, the first resistor is coupled between the output of the first operational amplifier and an inverting input of the second operational amplifier, the second resistor is coupled between the inverting input of the second operational amplifier and an output of the second operational amplifier, one end of the third resistor is coupled to a non-inverting input of the second operational amplifier, and one end of the fourth resistor is coupled between the non-inverting input of the second operational amplifier and a ground node,
the output of the second operational amplifier corresponds to one of the output nodes of the output units, and
the control circuit is configured to apply the refer

Assignees

• Kioxia Corp

Inventors

• Ota Kensuke
• Yamaguchi Marina
• Yoshikawa Masatoshi

Classifications

• G11C7/1066

  Output synchronization · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G06N20/00

  Machine learning · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title