Resistance change memory devices

US10374011B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10374011-B2
Application numberUS-201815986932-A
CountryUS
Kind codeB2
Filing dateMay 23, 2018
Priority dateJun 8, 2017
Publication dateAug 6, 2019
Grant dateAug 6, 2019

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Abstract

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A resistance change memory device includes a lower electrode, a ferroelectric material layer disposed on the lower electrode, a resistance switching material layer disposed on the ferroelectric material layer, and an upper electrode disposed on the resistance switching material layer.

First claim

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What is claimed is: 1. A resistance change memory device comprising: a lower electrode; a ferroelectric material layer disposed on the lower electrode; a resistance switching material layer disposed on the ferroelectric material layer; and an upper electrode disposed on the resistance switching material layer, wherein the resistance change memory device further comprises an interfacial insulation layer located between the upper electrode and the resistance switching material layer, and wherein formation or decomposition of the interfacial insulation layer is controlled by an external voltage between the lower electrode and the upper electrode. 2. The resistance change memory device of claim 1 , wherein the resistance switching material layer is disposed directly on the ferroelectric material layer. 3. The resistance change memory device of claim 1 , wherein a remanent polarization in the ferroelectric material layer applies an electrical attractive force or an electrical repulsive force to the resistance switching material layer. 4. The resistance change memory device of claim 1 , wherein after an applied voltage is removed from the upper electrode, a remanent polarization in the ferroelectric material layer induces charges to accumulate at an interface between the ferroelectric material layer and the resistance switching material layer. 5. The resistance change memory device of claim 4 , wherein the induced charges create an electric field across the resistance switching material layer that controls the movement of charges in the resistance switching material layer. 6. The resistance change memory device of claim 1 , wherein the resistance switching material layer includes movable oxygen ions. 7. The resistance change memory device of claim 6 , wherein when a positive voltage is applied to the upper electrode, then the upper electrode is combined with movable oxygen ions to form the interfacial insulation layer located between the resistance switching material layer and the upper electrode; and wherein when a negative voltage is applied to the upper electrode, then the movable oxygen ions are released from the interfacial insulation layer, which decomposes. 8. The resistance change memory device of claim 7 , wherein when a first remanent polarization having an orientation from the upper electrode toward the lower electrode is formed in the ferroelectric material layer by the positive voltage applied to the upper electrode, then the first remanent polarization reduces the number of movable oxygen ions that are released from the interfacial insulation layer; and wherein when a second remanent polarization having an orientation from the lower electrode toward the upper electrode is formed in the ferroelectric material layer by the negative voltage applied to the upper electrode, then the second remanent polarization reduces the amount of movable oxygen ions in the resistance switching material layer moving toward the upper electrode. 9. The resistance change memory device of claim 1 , wherein the resistance switching material layer includes a perovskite type oxide material. 10. The resistance change memory device of claim 9 , wherein the perovskite type oxide material includes at least one of a PCMO(Pr 1-x Ca x MnO 3 , where, 0<x<1) material, a LCMO(La 1-x Ca x MnO 3 , where, 0<x<1) material, a BSCFO(Ba 0.5 Sr 0.5 Co 0.8 Fe 0.2 O 3-δ ) material, a YBCO(YBa 2 Cu 3 O 7-x , where, 0<x<1) material, a (Ba,Sr)TiO 3 (Cr, Nb-doped) material, a SrZrO 3 (Cr,V-doped) material, a (La, Sr)MnO 3 material, a Sr 1-x La x TiO 3 (where, 0<x<1) material, a La 1-x SrxFeO 3 (where, 0<x<1) material, a La 1-x Sr x CoO 3 (where, 0<x<1) material, a SrFeO 2.7 material, a LaCoO 3 material, a RuSr 2 GdCu 2 O 3 material and a YBa 2 Cu 3 O 7 material. 11. The resistance change memory device of claim 1 , wherein the resistance switching material layer includes a metal oxide material having a nonstoichiometric composition. 12. The resistance change memory device of claim 11 , wherein the metal oxide material includes at least one of a titanium oxide material, an aluminum oxide material, a nickel oxide material, a copper oxide material, a zirconium oxide material, a manganese oxide material, a hafnium oxide material, a tungsten oxide material, a tantalum oxide material, a niobium oxide material and a ferrum oxide material. 13. The resistance change memory device of claim 1 , wherein the ferroelectric material layer includes a metal oxide material having a perovskite crystalline structure. 14. The resistance change memory device of claim 1 , wherein the ferroelectric material layer includes at least one of a hafnium oxide material, a zirconium oxide material and a hafnium zirconium oxide material. 15. The resistance change memory device of claim 1 , wherein the upper electrode includes at least one of an aluminum (Al) material, a molybdenum (Mo) material, a platinum (Pt) material, a titanium (Ti) material, a nickel (Ni) material, a tungsten (W) material, a tantalum (Ta) material, a titanium nitride (TiN) material and a tungsten silicide (WSi 2 ) material. 16. A resistance change memory device comprising: a lower electrode; a ferroelectric material layer disposed on the lower electrode having a remanent polarization; a resistance switching material layer including movable oxygen ions disposed on the ferroelectric material layer; and an upper electrode disposed on the resistance switching material layer, wherein a resistance value of the resistance change memory device is determined according to formation or decomposition of an interfacial insulation layer located between the upper electrode and the resistance switching material layer when an external voltage is applied to the upper electrode while the lower electrode is grounded. 17. The resistance change memory device of claim 16 , wherein after the external voltage is removed, the remanent polarization induces charges to accumulate at an interface between the ferroelectric material layer and the resistance switching material layer. 18. The resistance change memory device of claim 17 , wherein the accumulated charges create an electric field across the resistance switching material layer that control movement of the movable oxygen ions in the resistance switching material layer. 19. The resistance change memory device of claim 16 , wherein when the external voltage has a first polarity, then the upper electrode is combined with movable oxygen ions to form the interfacial insulation layer; and wherein when the external voltage has a second polarity, then movable oxygen ions are released from the interfacial insulation layer, which decomposes. 20. The resistance change memory device of claim 19 , wherein when the remanent polarization in the ferroelectric material layer has a direction from the upper electrode toward the lower electrode, then the remanent polarization reduces the number of movable oxygen ions released from the interfacial insulation layer; and wherein when the remanent polarization in the ferroelectric material layer has a direction from the lower electrode toward the upper electrode, then the remanent polarization reduces the amount of movable oxygen ions in the resistance switching material layer that move toward the upper electrode.

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What does patent US10374011B2 cover?
A resistance change memory device includes a lower electrode, a ferroelectric material layer disposed on the lower electrode, a resistance switching material layer disposed on the ferroelectric material layer, and an upper electrode disposed on the resistance switching material layer.
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H01L27/2463. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 06 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).