Scheduling configuration for deep learning networks

Patent metadata

Field	Value
Publication number	US-12033063-B2
Application number	US-202318174275-A
Country	US
Kind code	B2
Filing date	Feb 24, 2023
Priority date	Apr 28, 2017
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a cluster of distinct interconnected graphics processors, each graphics processor including a plurality of processing resources; and
processing circuitry to schedule operations to the cluster of distinct interconnected graphics processors, the processing circuitry configured to:
determine a traversal strategy for a deep learning neural network, the traversal strategy to be implemented via dispatch components of the graphics processors in the cluster of distinct interconnected graphics processors; and
convey the traversal strategy to the dispatch components of the graphics processors, the graphics processors configured to:
receive the traversal strategy and data for the deep learning neural network;
traverse a solution space of the deep learning neural network to score a plurality of solutions to schedule deep learning network execution on the plurality of processing resources of a graphics processor of the cluster of distinct interconnected graphics processors;
select a solution from the plurality of solutions to implement the deep learning network based on scores associated with the plurality of solutions; and
implement a workload schedule to assign tasks to the plurality of processing resources, wherein the workload schedule specifies a batch of grouped operations, the operations of the batch of grouped operations determined via a machine learning model based on historical data associated with the cluster of distinct interconnected graphics processors.

2. The apparatus of claim 1 , the solution to define a tile size for the deep learning network and a buffering level for the deep learning network.

3. The apparatus of claim 1 , the solution to define a data type for the deep learning network.

4. The apparatus of claim 1 , the solution to define a traversal order for the deep learning network.

5. The apparatus of claim 4 , wherein a scheduler component is configured to determine the traversal strategy for the deep learning neural network execution and forward the traversal strategy to the plurality of processing resources.

6. The apparatus of claim 5 , wherein the plurality of processing resources includes at least a first type of processing resource and a second type of processing resource that is different from the first type of processing resource.

7. The apparatus of claim 1 , wherein the plurality of processing resources is on a single integrated circuit.

8. The apparatus of claim 1 , wherein the traversal strategy is for a three-dimensional (3D) object divided into 3D tiles, each tile represented as a 3D cube in memory.

9. The apparatus of claim 1 , the graphics processors of the cluster of distinct interconnected graphics processors interconnected via first plurality of point-to-point interconnects.

10. The apparatus of claim 9 , at least a portion of the graphics processors of the cluster of distinct interconnected graphics processors additionally interconnected via a second plurality of interconnects to a host interface switch.

11. An electronic device, comprising:
a cluster of distinct interconnected graphics processors, each graphics processor including a plurality of processing resources; and
a processor, separate from the plurality of processing resources, to schedule operations to the cluster of distinct interconnected graphics processors, the processor configured to:
determine a traversal strategy for a deep learning neural network, the traversal strategy to be implemented via dispatch components of the graphics processors in the cluster of distinct interconnected graphics processors; and
convey the traversal strategy to the dispatch components of the graphics processors, the graphics processors configured to:
receive the traversal strategy and data for the deep learning neural network;
traverse a solution space of the deep learning neural network to score a plurality of solutions to schedule deep learning network execution on the plurality of processing resources of a graphics processor of the cluster of distinct interconnected graphics processors;
select a solution from the plurality of solutions to implement the deep learning network based on scores associated with the plurality of solutions; and
implement a workload schedule to assign tasks to the plurality of processing resources, wherein the workload schedule specifies a batch of grouped operations, the operations of the batch of grouped operations determined via a machine learning model based on historical data associated with the cluster of distinct interconnected graphics processors.

12. The electronic device of claim 11 , the solution to define a tile size for the deep learning network and a buffering level for the deep learning network.

13. The electronic device of claim 11 , the solution to define a data type for the deep learning network.

14. The electronic device of claim 11 , the solution to define a traversal order for the deep learning network.

15. The electronic device of claim 14 , wherein a scheduler component is configured to determine the traversal strategy for the deep learning neural network execution and forward the traversal strategy to the plurality of processing resources.

16. The electronic device of claim 15 , wherein the plurality of processing resources includes at least a first type of processing resource and a second type of processing resource that is different from the first type of processing resource.

17. The electronic device of claim 11 , wherein the plurality of processing resources is on a single integrated circuit.

18. The electronic device comprising of claim 11 , wherein the traversal strategy is for a three-dimensional (3D) object divided into 3D tiles, each tile represented as a 3D cube in memory.

19. The electronic device of claim 11 , the graphics processors of the cluster of distinct interconnected graphics processors interconnected via first plurality of point-to-point interconnects.

20. The electronic device of claim 19 , at least a portion of the graphics processors of the cluster of distinct interconnected graphics processors additionally interconnected via a second plurality of interconnects to a host interface switch.

Assignees

• Intel Corp

Inventors

• Ben-Avi Eran
• Zmora Neta
• Jacob Guy
• Faivishevsky Lev
• Dreyfuss Jeremie
• Bar-On Tomer
• Subag Jacob
• Fais Yaniv
• Hirsch Shira
• Weisel Orly
• Walter Zigi
• Oren Yarden

Classifications

• G06N3/0895

  Weakly supervised learning, e.g. semi-supervised or self-supervised learning · CPC title

• G06N3/098

  Distributed learning, e.g. federated learning · CPC title

• G06N3/09

  Supervised learning · CPC title

• G06N3/0442

  characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title