64-bit virtual addresses having metadata bit(s) and canonicality check that does not fail due to non-canonical values of metadata bit(s)

Patent metadata

Field	Value
Publication number	US-12032485-B2
Application number	US-202017133570-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Dec 23, 2020
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

Techniques to allow use of metadata in unused bits of virtual addresses are described. A processor of an aspect includes a decode circuit to decode a memory access instruction. The instruction to indicate one or more memory address operands that are to have address generation information and metadata. An execution circuit coupled with the decode circuit to generate a 64-bit virtual address based on the one or more memory address operands. The 64-bit virtual address having a bit 63 , an X-bit address field starting at a bit 0 to store an address generated from the address generation information, and one or more metadata bits to store the metadata. The execution circuit also to perform a canonicality check on the 64-bit virtual address that does not fail due to non-canonical values of the metadata stored in the one or more metadata bits. Other processors, methods, systems, and instructions are disclosed.

First claim

What is claimed is:

1. A processor comprising:
a decode circuit to decode a memory access instruction, the memory access instruction to indicate one or more memory address operands, the one or more memory address operands to have address generation information and metadata; and
an execution circuit coupled with the decode circuit, the execution circuit to:
generate a 64-bit virtual address based on the one or more memory address operands, the 64-bit virtual address having a bit 63 to indicate whether the 64-bit virtual address corresponds to user level or supervisor level, an X-bit address field starting at a bit 0 to store an address generated from the address generation information, and one or more metadata bits to store the metadata; and
perform a canonicality check on the 64-bit virtual address that does not fail due to non-canonical values of the metadata stored in the one or more metadata bits.

2. The processor of claim 1 , wherein the one or more metadata bits comprise a metadata field from a bit 62 to a bit X of the 64-bit virtual address.

3. The processor of claim 1 , wherein the execution circuit is to generate the 64-bit virtual address having more than eight metadata bits.

4. The processor of claim 1 , further comprising one or more registers to store one or more control bits to control one of a plurality of different possible numbers of the one or more metadata bits.

5. The processor of claim 4 , wherein the plurality of different possible numbers of the one or more metadata bits include six metadata bits and fifteen metadata bits.

6. The processor of claim 1 , wherein the execution circuit to perform the canonicality check is to check at least the bit 63 and a bit (X- 1 ) for canonicality but is not to check the one or more metadata bits for canonicality.

7. The processor of claim 1 , wherein the execution circuit is not to check any of bits [ 62 :X] for canonicality.

8. The processor of claim 1 , wherein the execution circuit is to make the one or more metadata bits canonical prior to the performance of the canonicality check and subsequent address translation.

9. The processor of claim 1 , further comprising one or more registers to store a user-level metadata bits control to control a number of the one or more metadata bits when the bit 63 is zero irrespective of a current processor privilege level.

10. The processor of claim 1 , further comprising one or more registers to store user-level metadata bits control to control a number of the one or more metadata bits for the user-level, wherein the number of the one or more metadata bits for the user-level is allowed to be more than (64-X)-bits, even when the processor is currently configured to use an X-bit address width.

11. The processor of claim 1 , further comprising one or more registers to store user-level metadata bits control to control a number of the one or more metadata bits for the user-level, wherein the number of the one or more metadata bits for the user-level is allowed to be more than 6-bits, even when the processor is currently configured to use a 57-bit address width.

12. The processor of claim 1 , wherein the execution circuit comprises:
address generation circuitry to generate the 64-bit virtual address;
circuitry to prevent the canonicality check from failing due to the non-canonical values of the metadata stored in the one or more metadata bits; and
canonicality check circuitry to perform the canonicality check on the 64-bit virtual address.

13. A method performed by a processor, the method comprising:
decoding a memory access instruction, the memory access instruction indicating one or more memory address operands, the one or more memory address operands having address generation information and metadata;
generating a 64-bit virtual address based on the one or more memory address operands, the 64-bit virtual address having a bit 63 to indicate whether the 64-bit virtual address corresponds to user level or supervisor level, an X-bit address field starting at a bit 0 storing an address generated from the address generation information, and one or more metadata bits storing the metadata; and
performing a canonicality check on the 64-bit virtual address that does not fail due to non-canonical values of the metadata stored in the one or more metadata bits.

14. The method of claim 13 , wherein the one or more metadata bits comprise a metadata field from a bit 62 to a bit X of the 64-bit virtual address.

15. The method of claim 13 , wherein the one or more metadata bits comprises either one of 6 bits or 15 bits.

16. The method of claim 13 , wherein to perform the canonicality check includes to check at least the bit 63 and a bit (X- 1 ) for canonicality, but not to check the one or more metadata bits for canonicality.

17. The method of claim 13 , wherein to perform the canonicality check includes to check at least the bit 63 and a bit (X- 1 ) for canonicality but not to check any of bits [ 62 :X] for canonicality.

18. The method of claim 13 , further comprising accessing a user-level metadata bits control to determine a number of the one or more metadata bits when the bit 63 is zero irrespective of a current processor privilege level.

19. The method of claim 13 , further comprising accessing user-level metadata bits control to determine a number of the one or more metadata bits for the user-level, wherein the number of the one or more metadata bits for the user-level is allowed to be more than (64-X)-bits, even when the processor is currently configured to use an X-bit address width.

20. A processor comprising:
a model specific register (MSR) having a bit position to store a first bit value;
a code segment (CS) register having a bit position to store a second bit value; and
circuitry to perform a canonicality check on a virtual address having bit positions 56 : 0 to store an address, wherein, if the first bit value and the second bit value are set to binary one, a third bit value is set to binary one, and the virtual address is used for a data access, the canonicality check on the virtual address will not fail due to bits stored in bit positions 62 : 57 of the virtual address being non-canonical.

21. The processor of claim 20 , wherein the bits stored in the bit positions 62 : 57 are to be omitted from the canonicality check.

22. The processor of claim 20 , wherein the circuitry to perform the canonicality check on the virtual address is to check at least bits 56 : 48 for canonicality when 4-level paging is active.

23. The processor of claim 20 , wherein the MSR is an Extended Feature Enable Register (EFER).

24. The processor of claim 20 , wherein the MSR is an Extended Feature Enable Register (EFER) having number 0×C0000080.

25. The processor of claim 20 , wherein the bit position of the code segment register is a CS.L bit position.

26. The processor of claim 25 , wherein the bit position of the model specific register is an EFER.LMA bit position.

27. The processor of claim 20 , wherein, if the first bit value, the second bit value, and the third bit value are set to binary one, the canonicality check on the virtual address will fail due to the bits stored in the bit positions 62 : 57 of the virtual address being non-canonical when the virtual address is used for a code fetch.

28. The processor of claim 20 , wherein, if the first bit va

Assignees

• Intel Corp

Inventors

• Shanbhogue Vedvyas
• Neiger Gilbert
• Robinson Stephen
• Baum Dan
• Gabor Ron

Classifications

• G06F12/1475

  in a virtual system, e.g. with translation means · CPC title

• G06F2212/683

  Invalidation · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title