Receive chain linearization via time-interleaved and polyphase mixing of interleaved paths

Patent metadata

Field	Value
Publication number	US-12028101-B2
Application number	US-202117520426-A
Country	US
Kind code	B2
Filing date	Nov 5, 2021
Priority date	Nov 5, 2021
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

Systems, devices, and methods related to time-interleaved polyphase linearization for a receive signal chain are provided. An example receive signal chain includes an input node to receive a radio frequency (RF) signal. The receive signal chain further includes a plurality of polyphase mixer circuitries including first mixers and first local oscillators to generate a plurality of phase-shifted downconverted signals based on the received RF signal. The receive signal chain further includes a first multiplexer to select one of the plurality of phase-shifted downconverted signals during each time slot of a plurality of time slots. The receive signal chain further includes signal conditioning circuitry comprising at least one nonlinear component. The signal conditioning circuitry conditions, during each time slot, a respective selected one of the plurality of phase-shifted downconverted signals to generate a conditioned signal. The receive signal chain further includes analog-to-digital-converter (ADC) downstream of the signal conditioning circuitry.

First claim

The invention claimed is:

1. An apparatus comprising:
an input node to receive an input signal;
a signal path coupled to the input node, the signal path comprising at least one nonlinear component; and
analog linearization circuitry coupled to the signal path, the analog linearization circuitry comprising:
a plurality of polyphase mixer circuitries coupled to the input node, the plurality of polyphase mixer circuitries comprising first mixers and first local oscillators; and
a first multiplexer comprising:
inputs coupled to outputs of the first mixers of the plurality of polyphase mixer circuitries; and
an output coupled to a first node on the signal path, wherein the first node is upstream of the at least one nonlinear component.

2. The apparatus of claim 1 , further comprising:
a low-noise amplifier (LNA) coupled to the input node,
wherein the signal path further comprises an analog-to-digital converter (ADC) downstream of the at least one nonlinear component.

3. The apparatus of claim 1 , wherein the at least one nonlinear component comprises at least one of a transimpedance amplifier, filtering circuitry, or a digital step attenuator.

4. The apparatus of claim 1 , wherein:
the analog linearization circuitry further comprises further polyphase mixer circuitry coupled between a second node and a third node on the signal path, wherein the second node and the third node are downstream of the at least one nonlinear component; and
the further polyphase mixer circuitry comprises:
second local oscillators;
a second multiplexer comprising inputs coupled to the second local oscillators; and
a second mixer comprising:
inputs coupled to an output of the second multiplexer and the second node on the signal path; and
an output coupled to the third node on the signal path.

5. The apparatus of claim 4 , wherein:
the first local oscillators of the plurality of polyphase mixer circuitries generate first local oscillation signals having different phases;
the second local oscillators of the further polyphase mixer circuitry generate second local oscillation signals having different phases; and
at least one of first local oscillation signals and one of the second local oscillation signals have opposite phases.

6. The apparatus of claim 4 , wherein:
the analog linearization circuitry further comprises path selection circuitry to generate a select signal in each time slot of a plurality of time slots;
the first multiplexer selectively couples, based on the select signal, one of the first local oscillators and an associated one of the first mixers to the signal path; and
the second multiplexer selectively couples, based on the select signal, one of the second local oscillators to the second mixer.

7. The apparatus of claim 4 , wherein the signal path further comprises summing circuitry coupled to the output of the second mixer, the summing circuitry comprising:
a demultiplexer comprising an input coupled to the third node; and
a plurality of capacitors coupled between an output of the demultiplexer and a fourth node on the signal path, wherein each of the plurality of capacitors is associated with one of the second local oscillators.

8. The apparatus of claim 4 , wherein:
the signal path further comprises a successive approximation analog-to-digital converter (SAR ADC) coupled to the output of the second mixer;
the SAR ADC comprises a capacitive digital-to-analog-converter (DAC); and
the capacitive DAC comprises:
a comparator; and
a plurality of parallel paths, each comprising:
a plurality of switches; and
a plurality of capacitors, each having a first plate coupled to an input of the comparator and a second plate coupled to a subset of the plurality of switches.

9. The apparatus of claim 8 , wherein:
the second multiplexer selectively couples each of the second local oscillators to the second mixer based on a respective one of select signals; and
the plurality of switches in each of the plurality of parallel paths are responsive to at least an associated one of the select signals of the second multiplexer.

10. The apparatus of claim 4 , wherein:
the signal path further comprises a pipelined analog-to-digital converter (ADC) coupled to the output of the second mixer;
the pipelined ADC comprises:
at least two ADC stages; and
residual amplifier circuitry coupled between the two ADC stages, the residual amplifier circuitry comprising:
an amplifier; and
one or more feedback capacitors coupled to the amplifier.

11. An analog frontend for a radio frequency (RF) transceiver, the analog frontend comprising:
an input node to receive an RF signal;
a plurality of polyphase mixer circuitries comprising first mixers and first local oscillators to generate a plurality of phase-shifted downconverted signals based on the received RF signal;
a first multiplexer to select one of the plurality of phase-shifted downconverted signals during each time slot of a plurality of time slots;
signal conditioning circuitry comprising at least one nonlinear component, the signal conditioning circuitry to condition, during each time slot, a respective selected one of the plurality of phase-shifted downconverted signals to generate a conditioned signal; and
analog-to-digital-converter (ADC) downstream of the signal conditioning circuitry.

12. The analog frontend of claim 11 , wherein the at least one nonlinear component of the signal conditioning circuitry comprises at least one of a transimpedance amplifier, filtering circuitry, or a digital step attenuator.

13. The analog frontend of claim 11 , further comprising:
further polyphase mixer circuitry comprising a second mixer, a second multiplexer, and second local oscillators to phase-shift, during each time slot, the conditioned signal to generate a phase-shifted conditioned signal.

14. The analog frontend of claim 13 , wherein:
the first local oscillators of the plurality of polyphase mixer circuitries generate first local oscillation signals having different phases;
the second local oscillators of the further polyphase mixer circuitry generate second local oscillation signals having different phases; and
at least one of first local oscillation signals and one of the second local oscillation signals have opposite phases.

15. The analog frontend of claim 11 , wherein:
the ADC comprises a successive approximation register (SAR) analog-to-digital converter (ADC) comprising a capacitive digital-to-analog-converter (CAPDAC); and
the capacitive DAC comprises:
multiple sets of capacitors; and
a plurality of switches to selectively sample each phase-shifted conditioned signal onto one set of the multiple sets of capacitors.

16. A method for performing linearization on a receiver chain, the method comprising:
generating, via a plurality of polyphase mixer circuitries having first mixers and first local oscillators, a plurality of phase-shifted downconverted signals based on a radio frequency (RF) signal;
conditioning, via signal conditioning circuitry comprising at least one nonlinear component, each of the plurality of phase-shifted downconverted signals during a different time slot of a plurality of time slots to generate a respective one of a plurality of conditioned signals; and
phase-shifting, via further polyphase mixer circuitry comprising a second mixer and second local oscillators, each of the plurality of conditioned signals to generate a respective one of a plurality of phase-shifted conditioned signals; and
combining two or more phase-shifted conditioned signals of the plurality of phase-shifte

Assignees

• Analog Devices International Unlimited Co

Inventors

• Banerjee Debopam
• Lemkin Mark Alan

Classifications

• H04B1/123 Primary

  using adaptive balancing or compensation means (adaptive filter circuits and algorithms H03H) · CPC title