Correlated double sampling analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10128859-B1
Application number	US-201815899883-A
Country	US
Kind code	B1
Filing date	Feb 20, 2018
Priority date	Feb 20, 2018
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

Techniques are described to cancel kT/C sampling noise and residue amplifier sampling noise while also reducing power consumption in a pipelined analog-to-digital converter circuit.

First claim

The claimed invention is:

1. A method for performing correlated double sampling on an analog input signal coupled to a first ADC circuit and a digital-to-analog converter (DAC) circuit of a first stage of a pipelined analog-to-digital (ADC) circuit, the method comprising:
opening a switch to decouple the DAC circuit of the first stage from a bias voltage, the opening resulting in a noise charge onto the DAC circuit of the first stage;
sampling the noise charge;
loading an output of the first ADC circuit of the first stage onto the DAC circuit of the first stage to generate a residue charge;
sampling the combination of the noise charge and the residue charge; and
subtracting the sampled noise charge from the sampled combination of the noise charge and the residue charge to cancel the noise charge.

2. The method of claim 1 , wherein sampling the noise charge includes:
filtering the noise charge.

3. The method of claim 2 , wherein filtering the noise charge includes:
settling a voltage; and
after settling the voltage, reducing a bandwidth to band limit the noise charge.

4. The method of claim 1 , further comprising:
amplifying the noise charge prior to sampling the noise charge; and
amplifying the residue charge prior to sampling the combination of the noise charge and the residue charge.

5. The method of claim 1 ,
wherein sampling the noise charge includes:
sampling the noise charge onto a second stage of the pipelined ADC circuit, and
wherein sampling the combination of the noise charge and the residue charge includes:
sampling the combination of the noise charge and the residue charge onto the second stage.

6. The method of claim 1 , wherein the pipelined ADC circuit is a differential ADC circuit, and wherein coupling an analog input signal includes:
coupling a differential analog input signal.

7. A method for performing correlated double sampling on an analog input signal coupled to an ADC circuit of a first stage of a pipelined analog-to-digital ADC circuit, the method comprising:
loading an output of the first ADC circuit of the first stage onto a DAC circuit of the first stage;
opening a switch to decouple the DAC circuit of the first stage from a bias voltage, the opening resulting in a noise charge onto the DAC circuit of the first stage;
sampling the noise charge;
coupling the analog input signal onto the DAC circuit of the first stage to generate a residue charge;
sampling the combination of the noise charge and the residue charge; and
subtracting the sampled noise charge from the sampled combination of the noise charge and the residue charge to cancel the noise charge.

8. The method of claim 7 , wherein sampling the amplified noise charge onto the first capacitor array of the DAC circuit of the second stage includes:
filtering the amplified noise charge.

9. The method of claim 8 , wherein filtering the amplified noise charge includes:
settling a voltage; and
after settling the voltage, reducing a bandwidth to band limit the noise charge.

10. The method of claim 7 , further comprising:
amplifying the noise charge prior to sampling the noise charge; and
amplifying the residue charge prior to sampling the combination of the noise charge and the residue charge.

11. The method of claim 7 ,
wherein sampling the noise charge includes:
sampling the noise charge onto a second stage of the pipelined ADC circuit, and
wherein sampling the combination of the noise charge and the residue charge includes:
sampling the combination of the noise charge and the residue charge onto the second stage.

12. The method of claim 7 , wherein the pipelined ADC circuit is a differential ADC circuit, and wherein coupling an analog input signal includes:
coupling a differential analog input signal.

13. A pipelined analog-to-digital converter (ADC) circuit for performing correlated double sampling on an analog signal coupled to a first stage of the pipelined ADC circuit, the first stage including a first ADC circuit and a digital-to-analog converter (DAC) circuit coupled to an output if the first ADC circuit, the pipelined ADC circuit comprising:
a control circuit configured to control operation of a plurality of switches to:
open a switch to decouple the DAC circuit of the first stage from a bias voltage, the opening resulting in a noise charge onto the DAC circuit of the first stage;
sample the noise charge;
load an output of the first ADC circuit of the first stage onto the DAC circuit of the first stage to generate a residue charge;
sample the combination of the noise charge and the residue charge; and
subtract the sampled noise charge from the sampled combination of the noise charge and the residue charge to cancel the noise charge.

14. The pipelined ADC circuit of claim 13 , further comprising:
a dynamic filter, wherein the control circuit configured to control operation of the plurality of switches to sample the noise charge is configured to control operation of the plurality of switches to:
filter the noise charge using the dynamic filter.

15. The pipelined ADC circuit of claim 13 , further comprising:
an amplifier circuit, wherein the control circuit configured to control operation of the plurality of switches to:
amplify the noise charge prior to sampling the noise charge; and
amplify the residue charge prior to sampling the combination of the noise charge and the residue charge.

16. The pipelined ADC circuit of claim 13 , wherein the analog input signal is a differential analog input signal, and wherein the pipelined ADC circuit is arranged in a differential configuration.

17. A pipelined analog-to-digital converter (ADC) circuit for performing correlated double sampling on an analog input signal coupled to a first ADC circuit of a first stage of the pipelined ADC circuit, the first stage including the first ADC circuit and a digital-to-analog converter (DAC) circuit coupled to an output of the first ADC circuit, the pipelined ADC circuit comprising:
a control circuit configured to control operation of a plurality of switches to:
load an output of the first ADC circuit of the first stage onto the DAC circuit of the first stage;
open a switch to decouple the DAC circuit of the first stage from a bias voltage, the opening resulting in a noise charge onto the DAC circuit of the first stage;
sample the noise charge;
couple the analog signal onto the DAC circuit of the first stage to generate a residue charge;
sample the combination of the noise charge and the residue charge; and
subtract the sampled noise charge from the sampled combination of the noise charge and the residue charge to cancel the noise charge.

18. The pipelined ADC circuit of claim 17 , further comprising:
a dynamic filter, wherein the control circuit configured to control operation of the plurality of switches to sample the noise charge is configured to control operation of the plurality of switches to:
filter the noise charge using the dynamic filter.

19. The pipelined ADC circuit of claim 17 , further comprising:
an amplifier circuit, wherein the control circuit configured to control operation of the plurality of switches to:
amplify the noise charge prior to sampling the noise charge; and
amplify the residue charge prior to sampling the combination of the noise charge and the residue charge.

20. The pipelined ADC circuit of claim 17 , wherein the analog input signal is a differential analog input signal, and wherein the pipelined ADC circuit is arranged in a differe

Assignees

• Analog Devices Global Unlimited Co

Inventors

• Rajasekhar Sanjay
• Maurino Roberto Sergio Matteo

Classifications

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/804

  with charge redistribution · CPC title

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title

• H03M1/0607 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title