Digital-to-analog converter, digital-to-analog conversion system, electronic system, base station and mobile device

Patent metadata

Field	Value
Publication number	US-12028090-B2
Application number	US-201917754310-A
Country	US
Kind code	B2
Filing date	Dec 23, 2019
Priority date	Dec 23, 2019
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

A digital-to-analog converter is provided. The digital-to-analog converter includes a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter includes a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells includes a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells include different numbers of inverter cells. The digital-to-analog converter additionally includes an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

First claim

What is claimed is:

1. A digital-to-analog converter, comprising:
a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals;
a plurality of groups of inverter cells, wherein each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals, wherein the inverter cells comprise a respective inverter circuit configured to invert the respective delayed digital input signal, and wherein the plurality of groups of inverter cells comprise different numbers of inverter cells; and
an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

2. The digital-to-analog converter of claim 1 , wherein at least one of the inverter cells comprises:
a cell output; and
a capacitive element configured to supply an analog cell output signal to the cell output based on the inverted delayed digital input signal output by the inverter circuit of the at least one of the inverter cells.

3. The digital-to-analog converter of claim 2 , wherein the at least one of the inverter cells further comprises:
a resistive element coupled between the inverter circuit and the capacitive element.

4. The digital-to-analog converter of claim 1 , wherein at least one of the inverter cells comprises:
a cell output; and
a resistive element configured to supply an analog cell output signal to the cell output based on the inverted delayed digital input signal output by the inverter circuit of the at least one of the inverter cells.

5. The digital-to-analog converter of claim 4 , further comprising:
a capacitive element coupled between the plurality of groups of inverter cells and the output, wherein the capacitive element is configured to generate the analog output signal based on the analog signals of the plurality of groups of inverter cells.

6. The digital-to-analog converter of claim 1 , wherein the plurality of groups of inverter cells form a finite impulse response filter, and wherein the numbers of inverter cells of the plurality of groups of inverter cells are selected based on desired filter coefficients of the finite impulse response filter.

7. The digital-to-analog converter of claim 1 , wherein the delay circuit comprises a plurality of delay elements configured to iteratively delay the digital input signal based on the clock signal.

8. The digital-to-analog converter of claim 7 , wherein the delay elements are flip-flop circuits.

9. The digital-to-analog converter of claim 1 , wherein the digital-to-analog converter is a 1 bit digital-to-analog converter.

10. A digital-to-analog conversion system, comprising:
a plurality of digital-to-analog converters according to claim 1 ; and
a clock generator circuit configured to output a plurality of phase-shifted clock signals, wherein the respective delay circuit of each of the plurality of digital-to-analog converters is configured to iteratively delay a respective digital input signal based on a different one of the plurality of phase-shifted clock signals.

11. The digital-to-analog conversion system of claim 10 , further comprising:
a system output configured to output a combined analog output signal based on the analog output signals of the plurality of digital-to-analog converters.

12. The digital-to-analog conversion system claim 10 , wherein the delay circuits of the plurality of digital-to-analog converters are configured to iteratively delay the same digital input signal.

13. An electronic system, comprising:
at least one digital-to-analog converter according to claim 1 , wherein the digital input signal is a digital calibration signal;
an analog-to-digital converter coupled to the at least one digital-to-analog converter and configured to generate digital output data based on the analog output signal of the at least one digital-to-analog converter; and
calibration circuitry configured to generate calibration data for the analog-to-digital converter based on the digital output data.

14. The electronic system of claim 13 , wherein the at least one digital-to-analog converter, the analog-to-digital converter and the calibration circuitry are implemented in the same semiconductor chip.

15. A base station, comprising:
an electronic system according to claim 13 , wherein the analog-to-digital converter is part of a receiver; and
at least one antenna element coupled to the receiver.

16. The base station of claim 15 , further comprising a transmitter configured to supply a radio frequency transmit signal to the antenna element for radiation to the environment.

17. A mobile device, comprising:
an electronic system according to claim 13 , wherein the analog-to-digital converter is part of a receiver; and
at least one antenna element coupled to the receiver.

18. The mobile device of claim 17 , further comprising a transmitter configured to supply a radio frequency transmit signal to the antenna element for radiation to the environment.

Assignees

• Intel Corp

Inventors

• Molina Albert
• Azadet Kameran
• Clara Martin
• Shin Hundo

Classifications

• H03M1/806

  with equally weighted capacitors which are switched by unary decoded digital signals · CPC title

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title

• H03H15/00

  Transversal filters (electromechanical filters H03H9/46, H03H9/70) · CPC title

• H03M1/808 Primary

  using resistors · CPC title

• H03M1/0626 Primary

  by filtering · CPC title