Amplifier

US12028023B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12028023-B2
Application numberUS-202117381652-A
CountryUS
Kind codeB2
Filing dateJul 21, 2021
Priority dateMar 13, 2019
Publication dateJul 2, 2024
Grant dateJul 2, 2024

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is an amplifier including: a first transistor connected to a signal input terminal; a second transistor connected to a signal output terminal; a wiring line configured to connect the first transistor and the second transistor to each other; and a variable inductor circuit which is electrically connected to the wiring line, and is grounded via a capacitor for DC current interruption, wherein the inductance value of the variable inductor circuit is set to an inductance value for canceling a parasitic capacitance between the first transistor and the second transistor.

First claim

Opening claim text (preview).

The invention claimed is: 1. An amplifier, comprising: a first transistor connected to a signal input terminal to which an input signal is to be input; a second transistor connected to a signal output terminal from which an output signal is to be output; a wiring line configured to cascade-connect the first transistor and the second transistor to each other; and a variable inductor circuit which is electrically connected to the wiring line, has an inductance value that is variable, and is grounded via a capacitor for DC current interruption, wherein the variable inductor circuit is configured to obtain a plurality of optimum inductance values for each frequency and each process variation of the first transistor and the second transistor in advance, obtain the optimum inductance value uniquely from the plurality of optimum inductance values, based on the value of the frequency and the process variation calculated from measurement data, and set the inductance value of the variable inductor circuit to the uniquely obtained optimum inductance value. 2. The amplifier according to claim 1 , wherein the variable inductor circuit is formed of a metal pattern formed on a semiconductor substrate. 3. The amplifier according to claim 1 , wherein the variable inductor circuit is formed of a transformer, and wherein the transformer includes: a primary-side inductor having one end connected to the wiring line, and the other end grounded via the capacitor; a secondary-side inductor coupled to the primary-side inductor with a coupling coefficient “k”; and a capacitive load which has a positive terminal connected to one end of the secondary-side inductor and a negative terminal connected to the other end of the secondary-side inductor, and is formed of a variable capacitance element. 4. The amplifier according to claim 2 , wherein the variable inductor circuit is formed of a transformer, and wherein the transformer includes: a primary-side inductor having one end connected to the wiring line, and the other end grounded via the capacitor; a secondary-side inductor coupled to the primary-side inductor with a coupling coefficient “k”; and a capacitive load which has a positive terminal connected to one end of the secondary-side inductor and a negative terminal connected to the other end of the secondary-side inductor, and is formed of a variable capacitance element. 5. The amplifier according to claim 3 , wherein the variable capacitance element is formed of a diode. 6. The amplifier according to claim 4 , wherein the variable capacitance element is formed of a diode. 7. The amplifier according to claim 1 , wherein each of the first transistor and the second transistor is formed of a bipolar transistor, and wherein the wiring line is configured to connect a collector terminal of the first transistor and an emitter terminal of the second transistor to each other. 8. The amplifier according to claim 2 , wherein each of the first transistor and the second transistor is formed of a bipolar transistor, and wherein the wiring line is configured to connect a collector terminal of the first transistor and an emitter terminal of the second transistor to each other. 9. The amplifier according to claim 3 , wherein each of the first transistor and the second transistor is formed of a bipolar transistor, and wherein the wiring line is configured to connect a collector terminal of the first transistor and an emitter terminal of the second transistor to each other. 10. The amplifier according to claim 4 , wherein each of the first transistor and the second transistor is formed of a bipolar transistor, and wherein the wiring line is configured to connect a collector terminal of the first transistor and an emitter terminal of the second transistor to each other. 11. The amplifier according to claim 5 , wherein each of the first transistor and the second transistor is formed of a bipolar transistor, and wherein the wiring line is configured to connect a collector terminal of the first transistor and an emitter terminal of the second transistor to each other. 12. The amplifier according to claim 6 , wherein each of the first transistor and the second transistor is formed of a bipolar transistor, and wherein the wiring line is configured to connect a collector terminal of the first transistor and an emitter terminal of the second transistor to each other. 13. The amplifier according to claim 1 , wherein each of the first transistor and the second transistor is formed of a field effect transistor, and wherein the wiring line is configured to connect a drain terminal of the first transistor and a source terminal of the second transistor to each other. 14. The amplifier according to claim 2 , wherein each of the first transistor and the second transistor is formed of a field effect transistor, and wherein the wiring line is configured to connect a drain terminal of the first transistor and a source terminal of the second transistor to each other. 15. The amplifier according to claim 3 , wherein each of the first transistor and the second transistor is formed of a field effect transistor, and wherein the wiring line is configured to connect a drain terminal of the first transistor and a source terminal of the second transistor to each other. 16. The amplifier according to claim 4 , wherein each of the first transistor and the second transistor is formed of a field effect transistor, and wherein the wiring line is configured to connect a drain terminal of the first transistor and a source terminal of the second transistor to each other. 17. The amplifier according to claim 5 , wherein each of the first transistor and the second transistor is formed of a field effect transistor, and wherein the wiring line is configured to connect a drain terminal of the first transistor and a source terminal of the second transistor to each other. 18. The amplifier according to claim 6 , wherein each of the first transistor and the second transistor is formed of a field effect transistor, and wherein the wiring line is configured to connect a drain terminal of the first transistor and a source terminal of the second transistor to each other.

Assignees

Inventors

Classifications

  • A transformer being used as coupling element between two amplifying stages · CPC title

  • H03F1/565Primary

    using inductive elements · CPC title

  • with MOSFET's · CPC title

  • the amplifier being a radio frequency amplifier · CPC title

  • by use of neutralising means · CPC title

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Frequently asked questions

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What does patent US12028023B2 cover?
Provided is an amplifier including: a first transistor connected to a signal input terminal; a second transistor connected to a signal output terminal; a wiring line configured to connect the first transistor and the second transistor to each other; and a variable inductor circuit which is electrically connected to the wiring line, and is grounded via a capacitor for DC current interruption, wh…
Who is the assignee on this patent?
Mitsubishi Electric Corp
What technology area does this patent fall under?
Primary CPC classification H03F1/565. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 02 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).