Source or drain structures with high germanium concentration capping layer

Patent metadata

Field	Value
Publication number	US-12027417-B2
Application number	US-202016913320-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	Jun 26, 2020
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

Integrated circuit structures having source or drain structures with a high germanium concentration capping layer are described. In an example, an integrated circuit structure includes source or drain structures including an epitaxial structure embedded in a fin at a side of a gate stack. The epitaxial structure has a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer. The lower semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface. The capping semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer; and
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer, wherein the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface, wherein the capping semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer, and wherein each of the capping semiconductor layers has a lateral width along a first direction perpendicular to a second direction from the first source or drain structure to the second source or drain structure, the lateral width greater than a lateral width of the corresponding lower semiconductor layer along the first direction.

2. The integrated circuit structure of claim 1 , wherein the capping semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises the germanium having an atomic concentration of greater than 55%.

3. The integrated circuit structure of claim 1 , wherein the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises the germanium having an atomic concentration of less than 30%.

4. The integrated circuit structure of claim 1 , wherein the capping semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises the boron having an atomic concentration of greater than 9E20 cm −3 .

5. The integrated circuit structure of claim 1 , further comprising:
a metal silicide layer on and in direct contact with the capping semiconductor layer of each of the epitaxial structures of the first and second source or drain structures.

6. The integrated circuit structure of claim 5 , wherein the metal silicide layer is a silicide of a silicon germanium layer having a composition substantially the same as the composition of the capping semiconductor layer.

7. The integrated circuit structure of claim 5 , further comprising:
a first conductive contact on a first portion of the metal silicide layer on the capping semiconductor layer of the epitaxial structure of the first source or drain structure; and
a second conductive contact on a second portion of the metal silicide layer on the capping semiconductor layer of the epitaxial structure of the second source or drain structure.

8. The integrated circuit structure of claim 1 , wherein the lower fin portion includes a portion of an underlying bulk single crystalline silicon substrate.

9. The integrated circuit structure of claim 1 , further comprising:
first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

10. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer; and
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer, wherein the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface, wherein the capping semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer, and wherein each of the capping semiconductor layers has a lateral width along a first direction perpendicular to a second direction from the first source or drain structure to the second source or drain structure, the lateral width greater than a lateral width of the corresponding lower semiconductor layer along the first direction.

11. The computing device of claim 10 , further comprising:
a memory coupled to the board.

12. The computing device of claim 10 , further comprising:
a communication chip coupled to the board.

13. The computing device of claim 10 , further comprising:
a camera coupled to the board.

14. The computing device of claim 10 , further comprising:
a battery coupled to the board.

15. The computing device of claim 10 , further comprising:
an antenna coupled to the board.

16. The computing device of claim 10 , wherein the component is a packaged integrated circuit die.

Assignees

• Intel Corp

Inventors

• Bomberger Cory
• Vishwanath Suresh
• Tolstova Yulia
• Patel Pratik
• Liao Szuya S
• Murthy Anand S

Classifications

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/01356

  the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence) · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/077 Primary

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title