High resolution analog to digital converter (ADC) with improved bandwidth

Patent metadata

Field	Value
Publication number	US-12021541-B2
Application number	US-202318129527-A
Country	US
Kind code	B2
Filing date	Mar 31, 2023
Priority date	Nov 8, 2019
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

First claim

What is claimed is:

1. An analog to digital converter (ADC) comprising:
a first capacitor that is operably coupled to a load and configured to produce a load voltage based on charging by a load current and a digital to analog converter (DAC) output current, wherein the ADC is coupled to the load via a single line;
a current sensor that is operably coupled and configured to sense a quantization noise current that is based on the load current and the DAC output current and to generate a signal that is representative of the quantization noise current;
first processing circuitry configured to operably coupled and configured to generate a first digital output signal that is representative of a difference between the load voltage and a reference voltage;
an N-bit digital to analog converter (DAC) that is operably coupled to the first processing circuitry and configured to generate the DAC output current based on the first digital output signal, wherein N is a positive integer, the DAC output current tracks the load current, and the load voltage tracks the reference voltage;
a second capacitor that is operably coupled to the current sensor and configured to produce a quantization noise voltage based on charging by the quantization noise current;
second processing circuitry operably coupled to the second capacitor and the current sensor and configured to generate a digital signal that is representative of a difference between the quantization noise voltage and a quantization noise reference voltage; and
a combining circuit that is operably coupled to the second processing circuitry and the first processing circuitry and configured to subtract the digital signal that is representative of a difference between the quantization noise voltage and a quantization noise reference voltage from the first digital output signal that is representative of a difference between the load voltage and a reference voltage to generate a second digital output signal.

2. The ADC of claim 1 , wherein the first processing circuitry further comprising:
a digital comparator operably coupled and configured to:
receive the load voltage via a first input of the digital comparator;
receive the reference voltage via a second input of the digital comparator; and
generate a third digital output signal that is representative of the difference between the load voltage and the reference voltage;

memory that stores operational instructions; and
one or more processing modules that is operably coupled to the digital comparator and the memory and configured to execute the operational instructions to process the third digital output signal to generate the first digital output signal that is representative of the difference between the load voltage and the reference voltage, wherein the first digital output signal includes a higher resolution than the third digital output signal.

3. The ADC of claim 2 , wherein the one or more processing modules is further configured to process the third digital output signal in accordance with performing band pass filtering or low pass filtering to generate the first digital output signal that is representative of the difference between the load voltage and the reference voltage.

4. The ADC of claim 1 , wherein the first processing circuitry further comprising:
a comparator operably coupled and configured to:
receive the load voltage via a first input of the comparator;
receive a reference voltage via a second input of the comparator; and
compare the load voltage to the reference voltage to generate a comparator output signal;

a digital circuit that is operably coupled to the comparator and configured to process the comparator output signal to generate a third digital output signal that is representative of a difference between the load voltage and the reference voltage;
memory that stores operational instructions; and
one or more processing modules that is operably coupled to the digital circuit and the memory and configured to execute the operational instructions to process the third digital output signal to generate the first digital output signal that is representative of the difference between the load voltage and the reference voltage, wherein the first digital output signal includes a higher resolution than the third digital output signal.

5. The ADC of claim 4 , wherein the one or more processing modules is further configured to process the third digital output signal in accordance with performing band pass filtering or low pass filtering to generate the first digital output signal that is representative of the difference between the load voltage and the reference voltage.

6. The ADC of claim 1 , wherein the second processing circuitry further comprising:
a digital comparator operably coupled and configured to:
receive the quantization noise voltage via a first input of the digital comparator;
receive the quantization noise reference voltage via a second input of the digital comparator; and
generate the digital signal that is representative of the difference between the quantization noise voltage and the quantization noise reference voltage.

7. The ADC of claim 1 , wherein the second processing circuitry further comprising:
a comparator operably coupled and configured to:
receive the load voltage via a first input of the comparator;
receive a reference voltage via a second input of the comparator; and
compare the load voltage to the reference voltage to generate a comparator output signal; and

a digital circuit that is operably coupled to the comparator and configured to process the comparator output signal to generate the digital signal that is representative of the difference between the quantization noise voltage and the quantization noise reference voltage.

8. The ADC of claim 1 , wherein the ADC implemented within an integrated circuit that is operably coupled to the load.

9. The ADC of claim 1 further comprising:
a decimation filter coupled to the combining circuit, wherein, when enabled, the decimation filter operably coupled and configured to process the second digital output signal to generate a third digital output signal having a lower sampling rate and a higher resolution than the second digital output signal.

10. The ADC of claim 1 , wherein the load includes an electrode, a sensor, or a transducer.

11. The ADC of claim 1 , wherein the ADC includes an operational bandwidth having an upper range of 200 kHz or 300 kHz.

12. The ADC of claim 1 , wherein the ADC is configured to consume less than 6 mW during operation.

13. An analog to digital converter (ADC) comprising:
a first capacitor that is operably coupled to a load and configured to produce a load voltage based on charging by a load current and a digital to analog converter (DAC) output current, wherein the ADC is coupled to the load via a single line, wherein the ADC implemented within an integrated circuit that is operably coupled to the load;
a current sensor that is operably coupled and configured to sense a quantization noise current that is based on the load current and the DAC output current and to generate a signal that is representative of the quantization noise current;
first processing circuitry configured to operably coupled and configured to generate a first digital output signal that is representative of a difference between the load voltage and a reference voltage;
an N-bit digital to analog converter (DAC) that is operably coupled to the first processing circuitry and configured to generate the DAC output current based on the first digital output signal, wherein N is a positive integer, the DAC output current tracks the load current, and

Assignees

• Sigmasense Llc

Inventors

• Huynh Phuong

Classifications

• H03M3/462

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/476 Primary

  Non-linear conversion systems · CPC title

• H03M3/422

  having one quantiser only · CPC title

• H03M1/34

  Analogue value compared with reference values (H03M1/48 takes precedence) · CPC title

• H03M1/0854

  of quantisation noise · CPC title