Method of manufacturing an array substrate wherein static electricity is discharged from an oxide semiconductor film

Patent metadata

Field	Value
Publication number	US-12021091-B2
Application number	US-202017298493-A
Country	US
Kind code	B2
Filing date	Sep 25, 2020
Priority date	Sep 25, 2019
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

The present disclosure provides an array substrate and a preparation method thereof, belonging to the field of display technology. The preparation method of the array substrate includes: providing a base substrate; forming a common electrode bonding line on one side of the base substrate; forming an oxide semiconductor material layer, and the oxide semiconductor material layer and the common electrode bonding line are located on the base substrate on the same side, and the oxide semiconductor material layer is electrically connected to at least part of the common electrode bonding line; the oxide semiconductor material layer is patterned to form an oxide semiconductor layer with multiple active layers, and the oxide semiconductor layer is The orthographic projection on the base substrate and the common electrode bonding line overlap at most parts of the orthographic projection on the base substrate, and any active layer and the common electrode bonding line are insulated from each other. The preparation method of the array substrate can avoid electrostatic breakdown of the array substrate during the preparation process.

First claim

What is claimed is:

1. A method of manufacturing an array substrate, comprising:
providing a base;
forming a plurality of conductive lines on the base;
forming an oxide semiconductor film on a side of the plurality of conductive lines away from the base, the oxide semiconductor film covering the plurality of conductive lines and being in direct contact with at least one conductive line, and the at least one conductive line being configured to discharge static electricity generated in the oxide semiconductor film; and
patterning the oxide semiconductor film by using a photoetching process to remove a portion of the oxide semiconductor film that is in direct contact with the at least one conductive line, and form an oxide semiconductor layer including active layers of a plurality of oxide thin film transistors, the oxide semiconductor layer and the at least one conductive line being insulated from each other.

2. The method of manufacturing the array substrate according to claim 1 , further comprising:
before forming the oxide semiconductor film, forming a gate conductive layer including gates of the plurality of oxide thin film transistors, the gate conductive layer and the plurality of conductive lines being located on the same side of the base;
forming a gate insulating film on a side of both the plurality of conductive lines and the gate conductive layer away from the base, the gate insulating film covering the plurality of conductive lines and the gate conductive layer; and
patterning the gate insulating film to form a gate insulating layer with at least one via hole, an orthogonal projection of the at least one via hole on the base being at least partially overlapped with an orthogonal projection of the at least one conductive line on the base;
wherein the oxide semiconductor film is in direct contact with the at least one conductive line through the at least one via hole.

3. The method of manufacturing the array substrate according to claim 2 , wherein a portion of a boundary of the orthogonal projection of the at least one conductive line on the base coincides with a portion of a boundary of the orthogonal projection of the at least one via hole on the base.

4. The method of manufacturing the array substrate according to claim 2 , wherein a material of the plurality of conductive lines includes a metal material; and
the plurality of conductive lines and the gate conductive layer are formed in a same patterning process.

5. The method of manufacturing the array substrate according to claim 1 , further comprising:
forming a source-drain conductive layer on a side of the oxide semiconductor layer away from the base, the source-drain conductive layer including sources and drains of the plurality of oxide thin film transistors that are in direct contact with respective active layers.

6. The method of manufacturing the array substrate according to claim 5 , wherein the array substrate has a display area and a bezel area located beside the display area; the source-drain conductive layer further includes at least one auxiliary lead that is in direct contact with the at least one conductive line;
the at least one conductive line and the at least one auxiliary lead are located in the bezel area;
the at least one conductive line is configured to transmit a common voltage signal to the display area, or to perform an electrostatic protection on the array substrate; and
the at least one auxiliary lead is configured to be connected in parallel with the at least one conductive line, so as to reduce a resistance of the at least one conductive line.

7. The method of manufacturing the array substrate according to claim 1 , wherein a material of the oxide semiconductor film includes one of zinc oxide, indium oxide, stannic oxide, indium zinc oxide, zinc tin oxide, aluminum zinc oxide, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide, and indium aluminum zinc oxide.

8. The method of manufacturing the array substrate according to claim 1 , wherein an orthogonal projection of the oxide semiconductor layer on the base is at most partially overlapped with an orthogonal projection of the at least one conductive line on the base.

Assignees

• Fuzhou Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Lin Bin
• Zeng Yong
• Huo Yazhou
• Li Liangliang
• Chen Zhouyu

Classifications

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D89/911 Primary

  using passive elements as protective elements · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title