Semiconductor device for a low-loss antenna switch

Patent metadata

Field	Value
Publication number	US-12021078-B2
Application number	US-202217853596-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Jul 12, 2019
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A semiconductor device is disclosed. The semiconductor device includes a substrate, a transistor, at least one isolation and at least one non-doped region. The substrate includes a lower portion. The transistor is disposed on the lower portion. The at least one isolation is adjacent to the transistor, and disposed on the lower portion. The at least one non-doped region is disposed between and adjacent to the isolation and the lower portion.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising a lower portion;
a transistor abutted with the lower portion;
at least one isolation adjacent to the transistor, and disposed on the lower portion; and
at least one non-doped region disposed between and adjacent to the at least one isolation and the lower portion.

2. The semiconductor device of claim 1 , further comprising:
at least one first metal layer disposed above the transistor and the at least one isolation; and
a resistor coupled to the transistor, and disposed between the at least one first metal layer and the at least one isolation.

3. The semiconductor device of claim 2 , further comprising:
at least one second metal layer disposed between the resistor and the at least one isolation.

4. The semiconductor device of claim 1 , further comprising:
at least one first metal layer disposed above the transistor and the at least one isolation; and
a resistor coupled to the transistor, and disposed above the at least one first metal layer.

5. The semiconductor device of claim 1 , wherein the at least one isolation comprises a first isolation and a second isolation, and
a lower part of the transistor is disposed between the first isolation and the second isolation.

6. The semiconductor device of claim 5 , wherein the at least one non-doped region comprises a first non-doped region and a second non-doped region, and
the lower part of the transistor is disposed between the first non-doped region and the second non-doped region.

7. The semiconductor device of claim 6 , further comprising:
a first resistor coupled to the transistor, and disposed above the first isolation; and
a second resistor disposed above the second isolation.

8. A semiconductor device, comprising:
a substrate comprising a lower portion;
a transistor abutted with the lower portion along a first direction;
a first non-doped region abutted with the lower portion along the first direction, and abutted with the transistor along a second direction different from the first direction; and
a first isolation abutted with the first non-doped region along the first direction, and abutted with the transistor along the second direction.

9. The semiconductor device of claim 8 , wherein a material of the first non-doped region is different from a material of the first isolation.

10. The semiconductor device of claim 8 , wherein the first non-doped region is a non-doped silicon region.

11. The semiconductor device of claim 8 , further comprising:
a second non-doped region abutted with the lower portion along the first direction, and abutted with the transistor along the second direction,
wherein a lower part of the transistor is disposed between the first non-doped region and the second non-doped region.

12. The semiconductor device of claim 11 , further comprising:
a second isolation abutted with the second non-doped region along the first direction, and abutted with the transistor along the second direction,
wherein the lower part of the transistor is disposed between the first isolation and the second isolation.

13. The semiconductor device of claim 12 , further comprising:
a first resistor coupled to the transistor and disposed directly above the first isolation along the first direction; and
a second resistor disposed directly above the second isolation along the first direction,
wherein the first resistor and the second resistor are separated from each other by a distance along the second direction.

14. The semiconductor device of claim 13 , wherein a width of the first resistor is smaller than a width of the first non-doped region along the second direction.

15. A semiconductor device, comprising:
a substrate comprising a lower portion;
a transistor abutted with the lower portion along a first direction;
a first non-doped silicon region abutted with the lower portion along the first direction, and abutted with the transistor along a second direction different from the first direction; and
a second non-doped silicon region abutted with the lower portion along the first direction, and abutted with the transistor along the second direction,
wherein a lower part of the transistor is disposed between the first non-doped silicon region and the second non-doped silicon region.

16. The semiconductor device of claim 15 , further comprising:
a first isolation abutted with the first non-doped silicon region along the first direction, and abutted with the transistor along the second direction,
wherein a material of the first isolation is different from a material of the first non-doped silicon region.

17. The semiconductor device of claim 16 , further comprising:
a second isolation abutted with the second non-doped silicon region along the first direction, and abutted with the transistor along the second direction,
wherein a material of the second isolation is different from a material of the second non-doped silicon region, and
the lower part of the transistor is disposed between the first isolation and the second isolation.

18. The semiconductor device of claim 17 , further comprising:
a first resistor disposed above the first isolation along the first direction; and
a second resistor disposed above the second isolation along the first direction,
wherein the first resistor and the second resistor are separated from each other by a distance along the second direction.

19. The semiconductor device of claim 18 , further comprising:
at least one first metal layer disposed above the transistor, the first isolation and the second isolation,
wherein the first resistor is disposed between the at least one first metal layer and the first isolation, and the second resistor is disposed between the at least one first metal layer and the second isolation.

20. The semiconductor device of claim 19 , further comprising:
at least one second metal layer disposed between the first resistor and the second resistor, and disposed between the first isolation and the second isolation.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Jin Jun-De
• Yeh Tzu-Jin

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W44/248

  for antennas · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title