Method for manufacturing package structure

US12021037B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12021037-B2
Application numberUS-202218077778-A
CountryUS
Kind codeB2
Filing dateDec 8, 2022
Priority dateNov 10, 2016
Publication dateJun 25, 2024
Grant dateJun 25, 2024

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for forming a package structure, comprising: forming a passivation layer having an opening; forming a first seed layer in the opening; filling the opening with a conductive layer over the first seed layer; bonding an integrated circuit die to the conductive layer over a first side of the passivation layer; removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer; and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer. 2. The method for forming the package structure as claimed in claim 1 , wherein the first seed layer covers a first surface of the passivation layer at the first side, and the second seed layer covers a second surface of the passivation layer at the second side. 3. The method for forming the package structure as claimed in claim 1 , wherein the opening gradually shrinks from the first side of the passivation layer to the second side of the passivation layer. 4. The method for forming the package structure as claimed in claim 1 , further comprising: forming a conductive structure over the second seed layer, wherein the integrated circuit die and the conductive structure are at opposite sides of the passivation layer. 5. The method for forming the package structure as claimed in claim 4 , further comprising: forming a first package layer surrounding the integrated circuit die; and forming a second package layer surrounding the first package layer and the passivation layer. 6. The method for forming the package structure as claimed in claim 5 , wherein the second package layer covers a sidewall of the passivation layer. 7. The method for forming the package structure as claimed in claim 5 , wherein the top surface of the conductive layer is lower than a top surface of the second package layer. 8. The method for forming the package structure as claimed in claim 5 , wherein a portion of the passivation layer vertically overlaps the second package layer but not the first package layer. 9. The method for forming the package structure as claimed in claim 4 , further comprising: forming a first package layer surrounding the integrated circuit die; and forming a second package layer surrounding the first package layer, wherein an interface between the first package layer and the second package layer adjoins a sidewall of the integrated circuit. 10. A method for forming a package structure, comprising: forming a passivation layer having an opening, wherein the passivation layer has a first sidewall exposed by the opening, and the first sidewall slopes downwardly from a first surface of the passivation layer to a second surface of the passivation layer opposite to the first surface; forming a first seed layer in a bottom portion of the opening and covering the first sidewall of the passivation layer; forming a conductive layer over the first seed layer; partially removing the first seed layer to expose a first portion of the first sidewall of the passivation layer; and forming a connector directly over the conductive layer and the first portion of the first sidewall of the passivation layer. 11. The method for forming the package structure as claimed in claim 10 , wherein the first seed layer covers a second portion of the first sidewall of the passivation layer and the first surface of the passivation layer. 12. The method for forming the package structure as claimed in claim 11 , wherein the second portion of the first sidewall of the passivation layer and the first surface of the passivation layer form an acute angle. 13. The method for forming the package structure as claimed in claim 10 , wherein the connector comprises: a second seed layer; and a conductive structure formed over the second seed layer, wherein the second seed layer continuously extending over the second surface of the passivation layer, the first portion of the first sidewall of the passivation layer, and a top surface of the conductive layer. 14. The method for forming the package structure as claimed in claim 13 , wherein the second seed layer is in direct contact with the first seed layer. 15. A method for forming a package structure, comprising: forming a redistribution layer over a carrier substrate; bonding an integrated circuit die electrically connected to the redistribution layer; forming a first package layer covering the integrated circuit die, wherein the first package layer is laterally spaced apart from an edge of the redistribution layer; forming a second package layer covering and surrounding the first package layer and the edge of the redistribution layer; removing the carrier substrate after the forming of the second package layer; and thinning the first package layer and the second package layer to expose the integrated circuit die. 16. The method for forming the package structure as claimed in claim 15 , wherein the redistribution layer comprises: a passivation layer; a first seed layer formed through the passivation layer; and a conductive layer formed over the first seed layer. 17. The method for forming the package structure as claimed in claim 16 , further comprising: partially removing the first seed layer to expose the conductive layer after removing the carrier substrate. 18. The method for forming the package structure as claimed in claim 17 , further comprising: forming a connector directly over and in contact with the conductive layer before thinning the first package layer and the second package layer. 19. The method for forming the package structure as claimed in claim 18 , wherein a lateral interface between the connector and the conductive layer is lower than a top surface of the passivation layer and higher than a bottom surface of the passivation layer. 20. The method for forming the package structure as claimed in claim 15 , further comprising: cutting through the first package layer and the redistribution layer to remove the second package layer after thinning the first package layer and the second package layer.

Assignees

Inventors

Classifications

  • Encapsulations, e.g. protective coatings · CPC title

  • the encapsulations exposing the passive side of the semiconductor body · CPC title

  • on active surfaces of flip-chip devices, e.g. underfills · CPC title

  • Package configurations · CPC title

  • batch processes · CPC title

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Frequently asked questions

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What does patent US12021037B2 cover?
Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method fur…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/05. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 25 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).