Plasma etching method and semiconductor device fabrication method including the same

Patent metadata

Field	Value
Publication number	US-12020903-B2
Application number	US-202217991024-A
Country	US
Kind code	B2
Filing date	Nov 21, 2022
Priority date	Oct 2, 2019
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A plasma etching method and a semiconductor device fabrication method, the plasma etching method including providing a source power having a first single pulse to an electrostatic chuck in order to generate a plasma on a substrate; providing a first bias power having a burst pulse different from the first single pulse to concentrate the plasma on the substrate; and providing a second bias power having a second single pulse the same as the first single pulse to accelerate the plasma toward the substrate.

First claim

What is claimed is:

1. A plasma etching method, comprising:
providing an electrostatic chuck with a source power to generate a plasma on a substrate; and
matching an impedance of the source power with an impedance of the plasma,
wherein matching the impedance of the source power with the impedance of the plasma includes:
obtaining a first impedance by providing a single pulse of the source power;
obtaining a second impedance by providing a two-level pulse of the source power;
comparing the first impedance and the second impedance with each other to obtain an impedance difference;
tuning a frequency of the source power in a low-level duration of the two-level pulse to obtain a first capacitance that removes an imaginary part of the impedance difference;
calculating a second capacitance that removes a real part of the impedance difference; and
matching the second impedance of the two-level pulse with the impedance of the plasma using the first capacitance and the second capacitance.

2. The plasma etching method as claimed in claim 1 , wherein the real part of the impedance difference is in inverse proportion to the second capacitance.

3. The plasma etching method as claimed in claim 1 , wherein:
the two-level pulse has a high-level duration having a power that is greater than a power of the low-level duration, and
the power of the high-level duration is the same as a power of the single pulse.

4. The plasma etching method as claimed in claim 1 , further comprising:
providing a first bias power to the electrostatic chuck to concentrate the plasma on the substrate; and
matching an impedance of the first bias power with the impedance of the plasma.

5. The plasma etching method as claimed in claim 1 , further comprising:
providing a second bias power to the electrostatic chuck to accelerate the plasma toward the substrate; and
matching an impedance of the second bias power with the impedance of the plasma.

6. A semiconductor device fabrication method, comprising:
allowing an electrostatic chuck to receive a substrate having an etch target layer; and
etching the etch target layer,
wherein etching the etch target layer includes:
providing a source power having a first single pulse to the electrostatic chuck to generate a plasma on the substrate;
providing a first bias power having a burst pulse different from the first single pulse to concentrate the plasma on the substrate; and
providing a second bias power having a second single pulse the same as the first single pulse to accelerate the plasma toward the substrate.

7. The semiconductor device fabrication method as claimed in claim 6 , wherein:
the etch target layer includes a mold dielectric layer, and
etching the etch target layer further includes removing a portion of the mold dielectric layer to form a plurality of channel holes.

8. The semiconductor device fabrication method as claimed in claim 7 , further comprising:
forming a vertical insulator and a first semiconductor pattern on an inner wall of each of the channel holes;
forming a channel structure on the vertical insulator, the first semiconductor pattern, and the substrate; and
etching a portion of the mold dielectric layer to form a trench, the portion of the mold dielectric layer being between the channel holes.

9. The semiconductor device fabrication method as claimed in claim 8 , further comprising:
forming a recess by removing a sacrificial layer of the mold dielectric layer, the sacrificial layer being exposed to the trench;
forming a horizontal insulator and a gate electrode in the recess;
forming a common source region in the substrate in the trench;
forming an electrode isolation pattern in the trench on the common source region; and
forming a contact plug and a bit line on the first semiconductor pattern and the channel structure.

10. The semiconductor device fabrication method as claimed in claim 6 , wherein the burst pulse includes a main pulse and a sub-pulse that has a pulse frequency different from a pulse frequency of the main pulse.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yonghee
• Han Byunghun
• Kang Hyeongmo
• Na Donghyeon
• Sung Dougyong
• Shim Seungbo
• Lee Minjae
• Choi Myungsun
• Hur Minyoung

Classifications

• H10P72/722

  Details of electrostatic chucks · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H03H7/38

  Impedance-matching networks · CPC title

• H01J2237/334

  Etching · CPC title