Operation method of nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-12020759-B2
Application number	US-202217878019-A
Country	US
Kind code	B2
Filing date	Jul 31, 2022
Priority date	Nov 4, 2021
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

An operation method of a nonvolatile memory device includes performing a 1-stage program step and a 1-stage verify step on a first word line, storing a first time stamp, performing the 1-stage program step and the 1-stage verify step on a second word line, storing a second time stamp, calculating a delay time based on the first time stamp and the second time stamp, determining whether the delay time is greater than a threshold value, adjusting at least one 2-stage verify voltage associated with the first word line from a first voltage level to a second voltage level based on the delay time, and performing a 2-stage program step and a 2-stage verify step on the first word line. A level of the at least one 1-stage verify voltage is lower than the second voltage level, and the second voltage level is lower than the first voltage level.

First claim

What is claimed is:

1. An operation method of a nonvolatile memory device which includes a plurality of memory blocks, each of the plurality of memory blocks including a plurality of strings connected between a bit line and a common source line, each of the plurality of strings including a plurality of memory cells connected in series, and the plurality of memory cells are respectively connected to a plurality of word lines stacked in a direction perpendicular to a substrate, the method comprising:
performing a 1-stage program operation on a first word line of the plurality of word lines, the 1-stage program operation on the first word line including:
a 1-stage program step in which a program voltage is applied to the first word line, and
a 1-stage verify step in which at least one 1-stage verify voltage of a plurality of 1-stage verify voltages is applied to the first word line after performing the 1-stage program step on the first word line;

storing a first time stamp indicating a time at which the 1-stage program operation for the first word line is completed;
after performing the 1-stage program operation, performing the 1-stage program operation on a second word line adjacent to the first word line, the 1-stage program operation on the second word line including:
the 1-stage program step in which a program voltage is applied to the second word line, and
the 1-stage verify step the second word line in which at least one 1-stage verify voltage of a plurality of 1-stage verify voltages is applied to the second word line after performing the 1-stage program step on the second word line;

storing a second time stamp indicating a time at which the 1-stage program operation for the second word line is completed;
calculating a delay time based on the first time stamp and the second time stamp;
determining whether the delay time is greater than or equal to a threshold value;
when it is determined that the delay time is greater than or equal to the threshold value, adjusting at least one 2-stage verify voltage of a plurality of 2-stage verify voltages associated with the first word line from a first voltage level to a second voltage level smaller than the first voltage level based on the delay time; and
after performing the 1-stage program operation on the second word line, performing a 2-stage program operation on the first word line, the 2-stage program operation on the first word line including:
a 2-stage program step in which a program voltage is applied to the first word line, and
a 2-stage verify step in which the adjusted at least one 2-stage verify voltage is applied to the first word line after performing the 2-stage program step on the first word line,

wherein a level of the at least one 1-stage verify voltage is lower than the second voltage level of the adjusted at least one 2-stage verify voltage corresponding to the at least one 1-stage verify voltage.

2. The method of claim 1 , wherein at least one memory cell connected to the first word line has one of an erase state and a plurality of program states by performing the 1-stage program operation and the 2-stage program operation,
wherein the plurality of 2-stage verify voltages include a first verify voltage and a second verify voltage,
wherein the first verify voltage is a reference voltage corresponding to a first program state of the plurality of program states and the second verify voltage is a reference voltage corresponding to a second program state different from the first program state,
wherein, when it is determined that the delay time is greater than the threshold value, a magnitude of a voltage level difference of the first verify voltage is different from a magnitude of a voltage level difference of the second verify voltage, and
wherein the voltage level difference of the first or second verify voltage is a difference between one of the plurality of 2-stage verify voltages and a corresponding one of the adjusted 2-stage verify voltages.

3. The method of claim 2 , wherein the second verify voltage of the second program state is greater than the first verify voltage of the first program state, and
wherein, when it is determined that the delay time is greater than the threshold value, the magnitude of the voltage level difference of the second verify voltage is greater than or equal to the magnitude of the voltage level difference of the first verify voltage.

4. The method of claim 1 , wherein the adjusting of the at least one 2-stage verify voltage for the first word line from the first voltage level to the second voltage level includes:
determining the second voltage level based on the delay time and a location of the first word line.

5. The method of claim 1 , wherein the threshold value is a first reference time, further comprising:
when the delay time is greater than or equal to the first reference time and is smaller than a second reference time, adjusting the at least one 2-stage verify voltage for the first word line from the first voltage level to the second voltage level; and
when the delay time is greater than or equal to the second reference time, adjusting the at least one 2-stage verify voltage for the first word line from the first voltage level to a third voltage level lower than the second voltage level and higher than the level of the at least one 1-stage verify voltage.

6. The method of claim 1 , wherein the adjusting of the at least one 2-stage verify voltage for the first word line from the first voltage level to the second voltage level includes:
referring to a verify voltage level look-up table including mapping information of the delay time and a 2-stage verify voltage level difference between the first voltage level and the second voltage level.

7. The method of claim 1 , wherein the adjusting of the at least one 2-stage verify voltage for the first word line from the first voltage level to the second voltage level includes:
computing, by machine learning logic, a 2-stage verify voltage level difference between the first voltage level and the second voltage level based on the delay time and access environment information; and
adjusting the at least one 2-stage verify voltage for the first word line from the first voltage level to the second voltage level based on the computed 2-stage verify voltage level difference.

8. The method of claim 7 , wherein the access environment information includes at least one of a location of a target block including the first word line, a location of a target string selection line corresponding to the first word line, a location of the first word line, an operating temperature of the nonvolatile memory device, the number of program/erase cycles, and a cell count.

9. The method of claim 1 , wherein the adjusting of the at least one 2-stage verify voltage for the first word line from the first voltage level to the second voltage level includes:
adjusting a develop period during which a voltage level of a sensing node connected to a memory cell connected to the first word line is changed through the bit line based on the delay time.

10. The method of claim 1 , wherein the adjusting of the at least one 2-stage verify voltage for the first word line from the first voltage level to the second voltage level includes:
adjusting a level of a read pass voltage to be applied to unselected memory cells based on the delay time.

11. The method of claim 1 , wherein the adjusting of the at least one 2-stage verify voltage for the first word line from the first voltage level to the second voltage level includes:
adjusting a precharge voltage level of the bit line connected to a memory cell connected to the first word line based on the delay time.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Jun-Ho
• Lee Juwon
• Kang Suk-Eun
• Lee Dogyeong
• Jeong Youngwook
• Joo Sang-Hyun

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3495

  Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/10

  Programming or data input circuits · CPC title