Double lockout in non-volatile memory

Patent metadata

Field	Value
Publication number	US-9875805-B2
Application number	US-201514928860-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	Jan 23, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A double lockout programming technique is provided having a hidden delay between programming and verification. A temporary lockout stage and a permanent lockout stage are provided for double lockout programming. The temporary lockout stage precedes the permanent lockout stage and is used to initially determine when a memory cell should be locked out a first time for one or more program pulses. When a memory cell initially passes verification for its target state, it is temporarily locked out from programming for one or more program pulses. The memory cell enters a permanent lockout stage where it is verified again for its target state. When the memory cell passes verification a second time, it is permanently locked out for programming during the current program phase. The memory cell may be programmed at one or more reduced program rates in the permanent lockout stage.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of bit lines;
a plurality of word lines;
a plurality of memory cells coupled to the plurality of bit lines and a first word line of the plurality of word lines, the plurality of memory cells including a first memory cell coupled to a first bit line of the plurality of bit lines; and
one or more control circuits configured to verify the first memory cell for a first verify level for a target data state after applying a first program pulse to the first word line and a first enable voltage to the first bit line, the one or more control circuits configured in response to the first memory cell passing verification for the first verify level to apply an inhibit voltage to the first bit line and apply a second program pulse to the first word line, the one or more control circuits configured to verify the first memory cell for second verify level for the target data state after applying the second program pulse, the one or more control circuits configured to permanently lockout the first memory cell from programming for the target data state in response to the first memory cell passing verification for the second verify level for the target data state after the second program pulse, the first verify level is lower than the second verify level.

2. The apparatus of claim 1 , wherein:
the one or more control circuits are configured to verify the first memory cell for the first verify level for the target data state after applying the second program pulse;
the one or more control circuits are configured to apply a third program pulse to the first word line and a second enable voltage to the first bit line in response to the first memory cell failing verification for the first verify level after the second program pulse, the second enable voltage is higher than the first enable voltage and lower than the inhibit voltage; and
the one or more control circuits are configured to apply the third program pulse to the first word line and a third enable voltage to the first bit line in response to the first memory cell passing verification for the first verify level and failing verification for the second verify level after the second program pulse, the third enable voltage is higher than the second enable voltage and lower than the inhibit voltage.

3. The apparatus of claim 2 , wherein:
the first enable voltage enables a first rate of programming of the first memory cell;
the second enable voltage enables a second rate of programming of the first memory cell that is less than the first rate of programming; and
the third enable voltage enables a third rate of programming that is less than the second rate of programming.

4. The apparatus of claim 3 , wherein:
the one or more control circuits are configured to apply the third program pulse to the first word line and the inhibit voltage to the first bit line in response to the first memory cell passing verification for the first verify level and passing verification for the second verify level after the second program pulse.

5. The apparatus of claim 1 , wherein:
the one or more control circuits are configured to verify the first memory cell for the second verify level for the target state after applying the first program pulse;
the one or more control circuits are configured in response to the first memory cell passing verification for the first verify level and passing verification for the second verify level after the first program pulse:
to apply the inhibit voltage to the first bit line and apply the second program pulse to the first word line; and
after applying the second program pulse, to verify the first memory cell for the first verify level and the second verify level.

6. The apparatus of claim 1 , further comprising:
one or more data latches coupled to the one or more control circuits;
wherein the one or more control circuits are configured to store in the one or more data latches a result of sensing at the first verify level and a result of sensing at the second verify level.

7. The apparatus of claim 1 , further comprising:
a three-dimensional non-volatile NAND memory array including the plurality of memory cells.

8. The apparatus of claim 1 , wherein:
the one or more control circuits are configured to verify the first memory cell for the first verify level for the target data state by applying a reference voltage to the first word line and sensing in response to the reference voltage after a first strobe time; and
the one or more control circuits are configured to verify the first memory cell for the second verify level for the target data state by applying the reference voltage to the first word line and sensing in response to the reference voltage after a second strobe time;
the first strobe time and the second strobe time are different and overlap.

9. A method, comprising:
applying a first program pulse to a first memory cell;
verifying the first memory cell for a first verify level and a second verify level for a target data state, the first verify level is lower than the second verify level;
if the first memory cell fails verification for the first verify level for the target data state, applying a second programming pulse and verifying the first memory cell for the first verify level and the second verify level;
if the first memory cell passes verification for the first verify level and fails verification for the second verify level for the target data state, inhibiting the first memory cell from programming for the second program pulse following the first program pulse;
after applying the second program pulse, verifying the first memory cell for the second verify level for the target data state;
if the first memory cell fails verification for the second verify level after applying the second program pulse, enabling the first memory cell for programming for a third program pulse;
and
if the first memory cell passes verification for the second verify level for the target state, inhibiting the first memory cell from programming for the third program pulse.

10. The method of claim 9 , further comprising subsequent to applying the first program pulse and prior to applying the second program pulse:
storing a result of verifying the first memory cell for the first verify level; and
storing a result of verifying the first memory cell for the second verify level.

11. The method of claim 10 , wherein:
verifying the first memory cell for the first verify level comprises applying a reference voltage to a word line connected to the first memory cell, applying a first bit line voltage to a bit line connected to the first memory cell and sensing in response to the reference voltage and first bit line voltage; and
verifying the first memory cell for the second verify level comprises applying the reference voltage to the word line connected to the first memory cell, applying a second bit line voltage to the bit line connected to the first memory cell, and sensing in response to the reference voltage and second bit line voltage.

12. The method of claim 9 , further comprising:
inhibiting the first memory cell from programming for the second program pulse in response to the first memory cell passing verification for the first verify level and passing verification for the second verify level; and
verifying the first memory cell for the first verify level and the second verify level after applying the second program pulse in response to the first memory cell passing verification for the first verify level and passing verification for the second verify level after applying the first program pulse.

13. The method of claim

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Tseng Huai-Yuan
• Dutta Deepanshu

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C2211/5621

  Multilevel programming verification · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title