Mechanism to automatically prioritize I/O for NFV workloads at platform overload

Patent metadata

Field	Value
Publication number	US-12020068-B2
Application number	US-202017022332-A
Country	US
Kind code	B2
Filing date	Sep 16, 2020
Priority date	Sep 16, 2020
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

Methods to automatically prioritize input/output (I/O) for Network Function Virtualization (NFV) workloads at platform overload and associated apparatus and mechanisms. During lab or runtime workload operations, various platform telemetry data are collected and analyzed to determine whether a current workload is uncore-sensitive—that is, sensitive to operations involving utilization of the uncore circuitry such as I/O-related operations, memory bandwidth utilization, LLC utilization, network traffic, core-to-core traffic etc. For uncore sensitive workloads, upon detection of a platform overload condition such as a thermal load approaching a TDP limit, the uncore circuitry is prioritized over the core circuitry such that the frequency of the core is reduced first. A closed-loop feedback mechanism is used to adjust the frequencies of the core and uncore under various workload conditions. The mechanism enables I/O throughput to be maintained for NFV workloads, while reducing the processor thermal load.

First claim

What is claimed is:

1. A method implemented in a platform including a processor having a core comprising a first portion of circuitry comprising a plurality of cores and a second portion of circuitry external to the core, comprising:
determining whether the second portion of circuitry is sensitive to a workload; and
during runtime execution of the workload on at least a portion of the plurality of cores,
adjusting a frequency of the second portion of circuitry relative to a frequency of the core as a function of whether the second portion of circuitry is determined to be sensitive to the workload.

2. The method of claim 1 , further comprising:
detecting a thermal operating condition of the processor has reached a threshold; and
in response thereto,
when the second portion of the circuitry is determined to be sensitive to the workload, reducing a frequency of the core.

3. The method of claim 1 , wherein the second portion of circuitry is determined to not be sensitive to the workload, and wherein in response to detecting a thermal operating condition of the processor has reached a threshold, reducing a frequency of the core and a frequency of the second portion of circuitry.

4. The method of claim 1 , wherein the second portion of circuitry includes input/output (I/O) circuitry and the platform includes at least one network interface controller (NIC) coupled to the I/O circuitry, further comprising determining whether the second portion of circuitry is sensitive to the workload by observing one or more NIC statistics during runtime execution of the workload.

5. The method of claim 1 , wherein each of the processor cores includes a Level 1 (L1) and a Level 2 (L2) cache operatively coupled to a Last Level Cache (LLC) in the second portion of circuitry, and wherein determining whether the second portion of circuitry is sensitive to the workload comprises observing core-to-core traffic during runtime execution of the workload.

6. The method of claim 1 , wherein each of the processor cores includes a Level 1 (L1) and a Level 2 (L2) cache operatively coupled to a Last Level Cache (LLC) in the second portion of circuitry, and wherein determining whether the second portion of circuitry is sensitive to the workload comprises observing LLC utilization during runtime execution of the workload.

7. The method of claim 1 , wherein the processor includes a memory controller having one or more memory channels coupled to one or more memory devices, and wherein determining whether the second portion of circuitry is sensitive to the workload comprises observing memory bandwidth utilization during runtime execution of the workload.

8. The method of claim 1 , wherein determining whether the second portion of circuitry is sensitive to the workload is performed via execution of software on one or more of the plurality of cores.

9. The method of claim 1 , wherein the platform further includes a baseboard management controller (BMC) coupled to the processor, further comprising employing the BMC to adjust frequencies of the core and second portion of circuitry.

10. The method of claim 1 , wherein the second portion of the circuitry is sensitive to a workload when the workload places a demand on the second portion of the circuitry that is higher than other non-sensitive workloads at a level where adjusting the frequency of the second portion of the circuitry relative to the core frequency provides a performance improvement.

11. The method of claim 1 , wherein the frequency of the core and the frequency of the second portion of circuitry are adjusted independently.

12. A system, comprising:
a processor having,
a core comprising a first portion of circuitry including a plurality of cores; and
a second portion of circuitry external to the core including one or more memory controllers and one or more input/output (I/O) interfaces;

memory, coupled to the one or more memory controllers;
a network interface, coupled to an I/O interface and having one or more ports at which packets are received; and
first and second software configured to be executed on the plurality of cores,
wherein execution of the first software enables the system to perform a workload, and wherein execution of the second software enables the system to adjust a frequency of the core and a frequency of the second portion of circuitry while performing the workload as a function of whether the second portion of circuitry is sensitive to the workload.

13. The system of claim 12 , wherein execution of the second portion of software further enables the system to:
determine whether the second portion of circuitry is sensitive to the workload;
detect a thermal operating condition of the processor has reached a threshold; and
in response thereto:
when the second portion of the circuitry is sensitive to the workload, reduce a frequency of the first portion of circuitry.

14. The system of claim 13 , wherein the second portion of circuitry is determined to not be sensitive to the workload, and wherein in response to detecting the thermal operating condition of the processor has reached the threshold, a frequency of the core and a frequency of the second portion of circuitry is reduced.

15. The system of claim 12 , wherein execution of the second portion of software determines whether the second portion of circuitry is sensitive to the workload by observing at least one statistic for the network interface.

16. The system of claim 12 , wherein each of the processor cores includes a Level 1 (L1) and a Level 2 (L2) cache operatively coupled to a Last Level Cache (LLC) in the second portion of circuitry, and wherein execution of the second portion of software determines whether the second portion of circuitry is sensitive to the workload by observing core-to-core traffic.

17. The system of claim 12 , wherein each of the processor cores includes a Level 1 (L1) and a Level 2 (L2) cache operatively coupled to a Last Level Cache (LLC) in the second portion of circuitry, and wherein execution of the second portion of software determines whether the second portion of circuitry is sensitive to the workload by observing LLC utilization.

18. The method of claim 12 , wherein execution of the second portion of software determines whether the second portion of circuitry is sensitive to the workload by observing memory bandwidth utilization.

19. The system of claim 12 , wherein the second portion of the circuitry is sensitive to a workload when the workload places a demand on the second portion of the circuitry that is higher than other non-sensitive workloads at a level where adjusting the frequency of the second portion of the circuitry relative to the core frequency provides a performance improvement.

20. One or more non-transitory machine-readable mediums having first software instructions stored thereon configured to be executed on a processor having a core comprising a first portion of circuitry associated with plurality of cores and a second portion of circuitry external to the core, the processor implemented in a system configured to perform a workload via execution of second software instructions on one or more of the plurality of cores, wherein execution of the first software instructions enables the system to:
during execution of the second software instructions to perform the workload,
process telemetry data obtained for the second portion of circuitry of the processor and determine whether the second portion of circuitry is sensitive to the workload;
adjust a frequency of the core

Assignees

• Intel Corp

Inventors

• Macnamara Chris
• Misra Amruta
• Browne John

Classifications

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F2212/1016

  Performance improvement · CPC title