Apparatus and Method for Thermal Management In A Multi-Chip Package

Patent metadata

Field	Value
Publication number	US-2016147291-A1
Application number	US-201414554384-A
Country	US
Kind code	A1
Filing date	Nov 26, 2014
Priority date	Nov 26, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . A processor comprising:
a first chip of a multi-chip package (MCP), wherein the first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold; and a conduit comprising a bi-directional pin to couple the first chip to the second chip within the MCP, wherein the conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip.

2 . The processor of claim 1 , wherein the first chip TC logic is to throttle at least one of the at least one core responsive to a first comparison that indicates that the first chip temperature exceeds the first threshold, and after the at least one core is throttled the first chip TC logic is to generate the first power adjustment signal responsive to a second comparison that indicates that the first chip temperature continues to exceed the first threshold.

3 . The processor of claim 1 , wherein adjustment of the second chip power consumption comprises reduction of power consumed by the second chip.

4 . The processor of claim 3 , wherein after the power consumed by the second chip is reduced, responsive to a third comparison that indicates that the first chip temperature is less than or equal to the first threshold, the first chip TC logic is to de-assert the first power adjustment signal.

5 . The processor of claim 1 , wherein the first chip is to receive, via the conduit, a second power adjustment signal responsive to an indication that a second chip temperature of the second chip exceeds a second threshold, wherein receipt of the second power adjustment signal by the first chip is to result in adjustment of a first chip power consumption of the first chip.

6 . The processor of claim 5 , wherein the first chip is to receive the receive the second power adjustment signal from the second chip after the second chip has adjusted a second chip power consumption of the second chip and when after adjustment of the second chip power consumption, the second chip temperature continues to exceed the second threshold.

7 . The processor of claim 5 , wherein after the second power adjustment signal is received by the first chip, responsive to the second chip temperature being less than or equal to the second threshold, the second power adjustment signal is de-asserted.

8 . The processor of claim 1 , further comprising at least one temperature sensor to measure the first chip temperature, wherein the at least one temperature sensor is to be located proximate to the first chip.

9 . A multi-chip package (MCP) comprising:
a first chip that includes a processor including at least one core and temperature control (TC) logic to generate a first power adjustment signal to be asserted at a second chip of the MCP responsive to a first indication that a first chip temperature of the first chip exceeds a first temperature threshold; a conduit comprising a bi-directional pin to couple the first chip and the second chip, wherein the conduit is to transport the first power adjustment signal from the first chip to the second chip; and the second chip including second chip logic to adjust a second chip power consumption of the second chip responsive to receipt of the first power adjustment signal.

10 . The MCP of claim 9 , wherein the second chip logic is to adjust the second chip power consumption by throttling second chip activity.

11 . The MCP of claim 9 , wherein after the second chip power consumption is adjusted, responsive to a second indication that the first chip temperature is less than or equal to the first temperature threshold, the TC logic is to de-assert the first power adjustment signal.

12 . The MCP of claim 9 , further comprising a third chip coupled to the first chip via the conduit, wherein the first power adjustment signal is to be asserted at the third chip of the MCP, via the conduit, responsive to the first indication that the first chip temperature of the first chip exceeds the first temperature threshold, and responsive to receipt of the first power adjustment signal the third chip is to adjust a third chip power consumption of the third chip.

13 . The MCP of claim 12 , wherein after the third chip power consumption is adjusted, responsive to a second comparison that indicates that the first chip temperature is less than or equal to the first threshold, the TC logic is to de-assert the first power adjustment signal.

14 . A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
monitoring a first temperature of a first chip of a multi-chip processor (MCP); responsive to a first indication that the first temperature exceeds a first threshold, throttling first chip power consumption of the first chip; after the first chip power consumption is throttled, responsive to a second indication that the first temperature continues to exceed the first threshold, asserting a first power adjustment signal by the first chip and transmitting the first power adjustment signal to a second chip of the MCP via a conduit comprising a bi-directional pin to couple the first chip and the second chip; and wherein responsive to receipt by the second chip of the first power adjustment signal, second chip power consumption of the second chip is to be throttled.

15 . The machine-readable medium of claim 14 , wherein the method includes responsive to a third indication that the first temperature is less than or equal to the first threshold after the first power adjustment signal has been transmitted, de-asserting by the first chip, the first power adjustment signal.

16 . The machine-readable medium of claim 14 , wherein the method further includes:
monitoring a second temperature associated with the second chip of the MCP; responsive to the second temperature being greater than a second threshold, throttling, by the second chip, second chip power consumption; and responsive to the second temperature being greater than the second threshold after the second chip power consumption is throttled, asserting by the second chip a second power adjustment signal including transmitting the second power adjustment signal from the second chip to the first chip via the conduit, wherein upon receipt by the first chip of the second power adjustment signal the first chip power consumption is to be throttled.

17 . The machine-readable medium of claim 16 , wherein the method further comprises after the second power adjustment signal is transmitted and responsive to the second temperature being less than or equal to the second threshold, de-asserting the second power adjustment signal.

18 . The machine-readable medium of claim 14 , wherein the first chip comprises a processor that includes a first core, and wherein throttling the first chip power consumption includes reduction of at least one of a first core clock frequency of the first core and a first core operating voltage of the first core.

19 . The machine-readable medium of claim 14 , wherein the first chip comprises a processor that includes a first core, and wherein throttling the first chip power consumption includes reduction of a duty cycle of the first core.

Assignees

• Intel Corp

Inventors

• Thomas Tessil
• Kandula Phani Kumar
• Krithivas Ramamurthy
• Chin Howard
• Steiner Ian M
• Garg Vivek

Classifications

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/32

  Means for saving power · CPC title

• G06F1/206

  comprising thermal management · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title