Temperature-based memory management

Patent metadata

Field	Value
Publication number	US-12019900-B2
Application number	US-202217697509-A
Country	US
Kind code	B2
Filing date	Mar 17, 2022
Priority date	Nov 15, 2018
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

Methods, systems, and devices for temperature-based memory management are described. A system may include a memory device and a host device. The host device may identify a temperature (e.g., of the memory device). The host device may determine a value for a parameter for operating the memory device—such as a timing, voltage, or frequency parameter—based on the temperature of the memory device. The host device may transmit signaling to the memory device or another component of the system based on the value of the parameter. In some cases, the host device may determine the temperature of the memory device based on an indication (e.g., provided by the memory device). In some cases, the host device may determine the temperature of the memory device based on a temperature of the host device or a temperature of another component of the system.

First claim

What is claimed is:

1. A method, comprising:
identifying a temperature of a memory device or of a host device coupled with the memory device;
determining a value of a voltage for operating the memory device based at least in part on the temperature;
transmitting signaling to a power supply for the memory device based at least in part on the value of the voltage; and
transmitting, based at least in part on transmitting the signaling to the power supply, a command to the memory device with a timing that is based at least in part on the value of the voltage.

2. The method of claim 1 , wherein the signaling to the power supply indicates the value of the voltage.

3. The method of claim 1 , further comprising:
sensing a temperature of the host device, wherein identifying the temperature of the memory device or the host device is based at least in part on sensing the temperature of the host device.

4. The method of claim 3 , further comprising:
identifying an offset between the temperature of the host device and the temperature of the memory device, wherein identifying the temperature of the memory device is based at least in part on the offset.

5. The method of claim 1 , further comprising:
determining that the temperature of the memory device or of the host device is below a threshold; and
determining the value of the voltage for operating the memory device based at least in part on determining that the temperature of the memory device or of the host device is below the threshold.

6. The method of claim 1 , wherein the memory device comprises cells having capacitive storage elements.

7. An apparatus, comprising:
logic operable to couple with a power supply for a memory device, the logic configured to:
identify a temperature of the memory device or of a host device coupled with the memory device;
determine a value of a voltage for operating the memory device based at least in part on the temperature;
transmit signaling to the power supply based at least in part on the value of the voltage; and
configure the host device to transmit, based at least in part on transmitting the signaling to the power supply, a command to the memory device with a timing that is based at least in part on the value of the voltage.

8. The apparatus of claim 7 , wherein the signaling to the power supply indicates the value of the voltage.

9. The apparatus of claim 7 , wherein the logic is further configured to:
sense a temperature of the host device, wherein identifying the temperature of the memory device or the host device is based at least in part on sensing the temperature of the host device.

10. The apparatus of claim 9 , wherein the logic is further configured to:
identify an offset between the temperature of the host device and the temperature of the memory device, wherein identifying the temperature of the memory device is based at least in part on the offset.

11. The apparatus of claim 7 , wherein the logic is further configured to:
determine that the temperature of the memory device or of the host device is below a threshold; and
determine the value of the voltage for operating the memory device based at least in part on determining that the temperature of the memory device or of the host device is below the threshold.

12. The apparatus of claim 7 , wherein the logic is a component of the host device.

13. The apparatus of claim 7 , wherein the memory device comprises cells having capacitive storage elements.

14. A system, comprising:
a memory device;
a host device coupled with the memory device;
one or more temperature sensors operable to indicate a temperature of the memory device or the host device coupled with the memory device; and
a power supply coupled with the memory device and operable to output a voltage based at least in part on the indicated temperature of the memory device or the host device,
wherein the host device is configured to transmit a command with a timing that is based at least in part on the voltage output by the power supply.

15. The system of claim 14 , wherein the one or more temperature sensors comprise a temperature sensor of the memory device.

16. The system of claim 14 , wherein the one or more temperature sensors comprise a temperature sensor of the host device.

17. The system of claim 14 , wherein the one or more temperature sensors comprise a temperature sensor of a coupling component coupled with the memory device and coupled with the host device.

18. The system of claim 14 , wherein the host device is further configured to:
receive the indication of the temperature from the one or more temperature sensors; and
transmit signaling to the power supply to output the voltage based at least in part on receiving the indication of the temperature, wherein transmitting the command is based at least in part on transmitting the signaling to the power supply.

Assignees

• Micron Technology Inc

Inventors

• Mayer Peter
• Hein Thomas
• Spirkl Wolfgang Anton
• Brox Martin
• Richter Michael Dieter

Classifications

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title